Nonvolatile static random access memory

• US 6,285,586 B1
• Filed: 10/16/2000
• Issued: 09/04/2001
• Est. Priority Date: 10/16/2000
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Kuo, Tung-Cheng, Lung, Hsiang-Lan, Chen, Shue-Shuen
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/688,767
• Time in Patent Office: 323 Days
• Field of Search: 365/185.08, 365/185.26, 365/185.14, 365/154
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A nonvolatile static random access memory adapted for a semiconductor substrate mainly comprises a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and further having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain is connected to a first bit line; an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line; a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal; a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal; and a read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line.

Claims

1. A nonvolatile static random access memory device adapted for a semiconductor substrate, comprising:

a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain terminal is connected to a first bit line;

an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line;

a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal;

a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal; and

a read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line.

2. The device according to claim 1, wherein the nonvolatile erasable programmable memory transistor comprises a MNOS transistor.

3. The device according to claim 1, wherein the nonvolatile erasable programmable memory transistor comprises a SNOS transistor.

4. The device according to claim 1, wherein the nonvolatile erasable programmable memory transistor comprises a SONOS transistor.

5. The device according to claim 1, wherein the nonvolatile erasable programmable memory transistor comprises a floating gate transistor.

6. The device according to claim 1, wherein a material of the charge storage layer comprises silicon nitride.

7. The device according to claim 1, wherein the first and second loader comprises resistor.

8. The device according to claim 1, wherein the data is stored in the charge storage layer before power is turned off, and the data stored in the charge storage layer is read out after power is turned on.

9. The device according to claim 8, wherein the data stored in the charge storage layer is maintained while power is turned off.

10. A nonvolatile static random access memory adapted for a semiconductor substrate, at least comprising:

a plurality of nonvolatile static random access memory cell, each nonvolatile static random access memory cell comprising;

a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain terminal is connected to a first bit line;

an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line;

a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal;

a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal; and

a plurality read control transistor, each read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line.

11. The memory according to claim 10, wherein the nonvolatile erasable programmable memory transistor comprises a MNOS transistor.

12. The memory according to claim 10, wherein the nonvolatile erasable programmable memory transistor comprises a SNOS transistor.

13. The memory according to claim 10, wherein the nonvolatile erasable programmable memory transistor comprises a SONOS transistor.

14. The memory according to claim 10, wherein the nonvolatile erasable programmable memory transistor comprises a floating gate transistor.

15. The memory according to claim 10, wherein a material of the charge storage layer comprises silicon nitride.

16. The memory according to claim 12, wherein the first and second loader comprises resistor.

17. The memory according to claim 12, wherein the data is stored in the charge storage layer before power is turned off, and the data stored in the charge storage layer is read out after power is turned on.

18. The memory according to claim 17, wherein the data stored in the charge storage layer is maintained while power is turned off.

19. A method for operating a nonvolatile static random access memory (NVSRAM) adapted for a nonvolatile static random access memory, the memory at least comprising:

a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain terminal is connected to a first bit line;

an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line;

a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal;

a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal; and

a read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line, comprising the step of;

(1) after power is turned on, the data stored in the charge storage layer of the nonvolatile erasable programmable memory transistor is read out in a nonvolatile operation mode and is transmitted to a data buffer region, and then, the data in the data buffer region is transmitted and stored in the NVSRAM cell in a SRAM operation mode;

(2) after the data is converted, the NVSRAM cell is operated in SRAM operation mode; and

(3) before power is turned off, the data stored in the NVSRAM cell is read out in SRAM mode and is transmitted to the data buffer region, and then, the data in the data buffer region is stored in the charge storage layer in nonvolatile operation mode.

20. The method according to claim 19, wherein the nonvolatile erasable programmable memory transistor comprises a MNOS transistor.

21. The method according to claim 19, wherein the nonvolatile erasable programmable memory transistor comprises a SNOS transistor.

22. The method according to claim 19, wherein the nonvolatile erasable programmable memory transistor comprises a SONOS transistor.

23. The method according to claim 19, wherein the nonvolatile erasable programmable memory transistor comprises a floating gate transistor.

24. The method according to claim 19, wherein a material of the charge storage layer comprises silicon nitride.

25. The method according to claim 19, wherein the first and second loader comprises resistor.

26. The method according to claim 19, wherein the data stored in the charge storage layer is maintained while power is turned off.