Dummy memory cells for high accuracy self-timing circuits in dual-port SRAM

• US 6,285,604 B1
• Filed: 01/06/2000
• Issued: 09/04/2001
• Est. Priority Date: 01/06/2000
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Meng-Fan
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/478,739
• Time in Patent Office: 607 Days
• Field of Search: 365/156, 365/200, 365/203, 365/189.08, 365/189.09, 365/205, 365/207, 365/202
• US Class Current: 365/200
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A dummy memory cells for high-accuracy self-timing circuit in dual-port SRAM is disclosed herein. The dummy memory cells mentioned above include a plurality of word lines, two pairs of bit lines, two pairs of load circuits and an array of dummy memory cells. The plurality of word lines is utilized to receive an access signal, the two pairs of load circuit are connected to the two pairs of bit lines respectively for applying to a voltage source. The array of dummy memory cells includes a first group of dummy memory cells and a second group of memory cells. Each of the first group of dummy memory cells having a first inverter assuming a first binary state is coupled to a first bit line, and has a first word line. The second group of dummy memory cells for acting as loading having a second inverter assuming a second binary state, each of the second inverter being coupled to the first bit line. Each of the second group of dummy memory cells having a second word line, the second word line of each of the second group of dummy memory cells is coupled to a source voltage level. The voltage on the two pairs of bit lines coupling to the array of dummy memory cells tracks the voltage drop on a normal bit line when the access signal arriving a normal memory cells coupled to the normal bit line.

Claims

1. A memory comprising:

a plurality of word lines for receiving an access signal;

a pair of bit lines;

a pair of load circuit connected to said pair of bit lines for applying thereto a voltage source; and

an array of memory cells, wherein voltage on said pair of bit lines coupling to said array of memory cells tracking voltage on a normal bit line when said access signal arriving a normal memory cells coupled to said normal bit line, said normal bit line being electrically coupled to said voltage source, each memory cell of said array of memory cells comprising two pairs of coupling transistors having a control terminal connected to a word line, and a pair of inverters connected in anti-parallel relationship to each other, each of said coupling transistors establishing a conductive path between one of said pair of bit lines and one of said pair of inverters responsive to said access signal to cause said pair of inverters to assume one of two binary states, gates of one of said pair of inverters being coupled to said voltage source, gates of the other of said pair of inverters being coupled to a source voltage level, a first control terminal of a first transistor of said two pairs of coupling transistors being coupled to a second control terminal of a second transistor of the other of said two pairs of coupling transistors.

2. The memory as claim 1, wherein said memory is a dual-port static random access memory (SRAM).

3. The memory as claim 1, wherein said load circuit comprises a first field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said load circuit comprises a second field effect transistor having a source-drain path connected between said voltage source and said array of memory cells.

4. The memory as claim 1, wherein said array of memory cells further comprising:

a first group of memory cells for providing current, said first group of memory cells acting as driver in said array of memory cells, each of said first group of memory cells having a first inverter assuming a first binary state, each of said first inverter being coupled to a first bit line of said pair of bit lines, each of said first group of memory cells having a first word line, said first word line of each of said first group of memory cells being coupled to access said access signal; and

a second group of memory cells for receiving said current, said second group of memory cells acting as loading in said array of memory cells, each of said second group of memory cells having a second inverter assuming a second binary state, each of said second inverter being coupled to said first bit line of said pair of bit lines, each of said second group of memory cells having a second word line, said second word line of each of said second group of memory cells being coupled to said source voltage level.

5. A memory comprising:

a plurality of word lines for receiving an access signal;

two pairs of bit lines;

two pairs of load circuit connected to said two pairs of bit lines respectively for applying thereto a voltage source; and

an array of memory cells, wherein voltage on said two pairs of bit lines coupling to said array of memory cells tracking voltage on a normal bit line when said access signal arriving a normal memory cells coupled to said normal bit line, said normal bit line being electrically coupled to said voltage source, each memory cell of said array of memory cells comprising two pairs of coupling transistors having a control terminal connected to a word line, and a pair of inverters connected in anti-parallel relationship to each other, each of said coupling transistors establishing a conductive path between one of said two pairs of bit lines and one of said pair of inverters responsive to said access signal to cause said pair of inverters to assume one of two binary states, gates of one of said pair of inverters being coupled to said voltage source, gates of the other of said pair of inverters being coupled to a source voltage level, a first control terminal of a first transistor of said two pairs of coupling transistors being coupled to a second control terminal of a second transistor of the other of said two pairs of coupling transistors.

6. The memory as claim 5, wherein said memory is a dual-port static random access memory (SRAM).

7. The memory as claim 5, wherein said two pairs of load circuits comprises a first field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said two pairs of load circuits comprises a second field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, said two pairs of load circuits comprises a third field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said two pairs of load circuits comprises a fourth field effect transistor having a source-drain path connected between said voltage source and said array of memory cells.

8. The memory as claim 7, wherein gate of said first field effect transistor being coupled to gate of said third field effect transistor, gate of said second field effect transistor, and gate of said fourth field effect transistor.

9. The memory as claim 5, wherein said array of memory cells further comprising:

a first group of memory cells for providing current, said first group of memory cells acting as driver in said array of memory cells, each of said first group of memory cells having a first inverter assuming a first binary state, each of said first inverter being coupled to a first bit line of said two pairs of bit lines, each of said first group of memory cells having a first word line, said first word line of each of said first group of memory cells being coupled to access said access signal; and

a second group of memory cells for receiving said current, said second group of memory cells acting as loading in said array of memory cells, each of said second group of memory cells having a second inverter assuming a second binary state, each of said second inverter being coupled to said first bit line of said two pairs of bit lines, each of said second group of memory cells having a second word line, said second word line of each of said second group of memory cells being coupled to said source voltage level.

10. A circuitry for emulating activity of bit lines of a memory, said circuitry comprising:

a plurality of word lines for receiving an access signal;

two pairs of dummy bit lines;

two pairs of load circuit connected to said two pairs of dummy bit lines respectively for applying thereto a voltage source;

an array of memory cells, wherein voltage on said two pairs of dummy bit lines coupling to said array of memory cells tracking voltage on bit lines when said access signal arriving a normal memory cells coupled to said bit lines, said normal bit line being electrically coupled to said voltage source, each memory cell of said array of memory cells comprising two pairs of coupling transistors having a control terminal connected to a word line, and a pair of inverters connected in anti-parallel relationship to each other, each of said coupling transistors establishing a conductive path between one of said two pairs of dummy bit lines and one of said pair of inverters responsive to said access signal to cause said pair of inverters to assume one of two binary states, gates of one of said pair of inverters being coupled to said voltage source, gates of the other of said pair of inverters being coupled to a source voltage level, a first control terminal of a first transistor of said two pairs of coupling transistors being coupled to a second control terminal of a second transistor of the other of said two pairs of coupling transistors, wherein said array of memory cells comprising;

a first group of memory cells for providing current, said first group of memory cells acting as driver in said array of memory cells, each of said first group of memory cells having a first inverter assuming a first binary state, each of said first inverter being coupled to a first dummy bit line of said two pairs of dummy bit lines, each of said first group of memory cells having a first word line, said first word line of each of said first group of memory cells being coupled to access said access signal; and

a second group of memory cells for receiving said current, said second group of memory cells acting as loading in said array of memory cells, each of said second group of memory cells having a second inverter assuming a second binary state, each of said second inverter being coupled to said first dummy bit line of said two pairs of dummy bit lines, each of said second group of memory cells having a second word line, said second word line of each of said second group of memory cells being coupled to said source voltage level;

control means for generating said access signal responding to voltage on said first bit line; and

trigger means for coupling said first bit line to said control means.

11. The circuit as claim 10, wherein said memory is a dual-port static random access memory (SRAM).

12. The circuit as claim 10, wherein said two pairs of load circuits comprises a first field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said two pairs of load circuits comprises a second field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, said two pairs of load circuits comprises a third field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said two pairs of load circuits comprises a fourth field effect transistor having a source-drain path connected between said voltage source and said array of memory cells.

13. The circuit as claim 12, wherein gate of said first field effect transistor being coupled to gate of said third field effect transistor, gate of said second field effect transistor, and gate of said fourth field effect transistor.

14. The circuit as claim 10, wherein said trigger means can be chosen from a group consisting:

inverter and Schmitt trigger.

15. A dummy memory comprising:

a plurality of word lines for receiving an access signal;

two pairs of bit lines;

two pairs of load circuit connected to said two pairs of bit lines respectively for applying thereto a voltage source; and

an array of dummy memory cells, wherein voltage on said two pairs of bit lines coupling to said array of memory cells tracking voltage on a normal bit line when said access signal arriving a normal memory cells coupled to said normal bit line, said normal bit line being electrically coupled to said voltage source, wherein said array of dummy memory cells comprising;

a first group of dummy memory cells for providing current, said first group of dummy memory cells acting as driver in said array of dummy memory cells, each of said first group of dummy memory cells having a first inverter assuming a first binary state, each of said first inverter being coupled to a first bit line of said two pairs of bit lines, each of said first group of dummy memory cells having a first word line, said first word line of each of said first group of dummy memory cells being coupled to access said access signal; and

a second group of dummy memory cells for receiving said current, said second group of dummy memory cells acting as loading in said array of memory cells, each of said second group of dummy memory cells having a second inverter assuming a second binary state, each of said second inverter being coupled to said first bit line of said two pairs of bit lines, each of said second group of dummy memory cells having a second word line, said second word line of each of said second group of dummy memory cells being coupled to a source voltage level.

16. The memory as claim 15, wherein said memory is a dual-port static random access memory (SRAM).

17. The memory as claim 15, wherein said two pairs of load circuits comprises a first field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said two pairs of load circuits comprises a second field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, said two pairs of load circuits comprises a third field effect transistor having a source-drain path connected between said voltage source and said array of memory cells, and wherein said two pairs of load circuits comprises a fourth field effect transistor having a source-drain path connected between said voltage source and said array of memory cells.

18. The memory as claim 17, wherein gate of said first field effect transistor being coupled to gate of said third field effect transistor, gate of said second field effect transistor, and gate of said fourth field effect transistor.

19. The memory as claim 15, wherein each of said array of dummy memory cells comprises two pairs of coupling transistors having a control terminal connected to a dummy word line, and a pair of inverters connected in anti-parallel relationship to each other, each of said coupling transistors establishing a conductive path between one of said two pairs of bit lines and one of said pair of inverters responsive to said access signal to cause said pair of inverters to assume one of two binary states, gates of one of said pair of inverters being coupled to said voltage source, gates of the other of said pair of inverters being coupled to said source voltage level, a first control terminal of a first transistor of said two pairs of coupling transistors being coupled to a second control terminal of a second transistor of the other of said two pairs of coupling transistors.