Memory system

• US 6,285,607 B1
• Filed: 10/20/2000
• Issued: 09/04/2001
• Est. Priority Date: 03/27/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Memory Corp. Plc (Torridon Plc)
• Inventors: Sinclair, Alan Welsh
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Yoha, Connie C.
• Application Number:
  US09/647,194
• Time in Patent Office: 319 Days
• Field of Search: 365/200, 365/230.01, 365/239, 365/189.01, 371/10.1, 371/10.2, 711/118
• US Class Current: 365/200
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory system (10) incorporating a plurality of memory devices (42) at least one of which has a defective location. Defects are mapped in a non-volatile memory (46). Data structures are divided into portions which are respectively stored in different ones of the memory devices (42). The controller (17) of the system accesses the non-volatile memory so as to generate on a per device basis an address corresponding to a non-defective location in that device. In this system, different addresses may therefore be applied to different ones of the devices (42) when a data structure is written to or read from the memory devices.

Claims

1. A memory system (10) comprising:

a plurality of memory devices (42), where at least one of the memory devices has a defective memory location;

defect mapping means (46) associated with each memory device having a defective location, for recording a representation of the location of the or each defective memory location;

a controller (17) for accessing the defect mapping means and for writing data structures to and reading data structures from the memory devices; and

host interface means (16) for conveying a host address and associated data structures between a host (12) and the controller;

the system being arranged and configured so that data structures are divided into portions which are respectively stored in different memory devices, and, in use, the controller (17) converts the host address to an intermediate address for use in accessing a memory location in each of a plurality of said devices, accesses the defect mapping means using said intermediate address and thereby generates on a per device basis, for each device of said plurality of devices, a physical address corresponding to a non-defective location within that device by incrementing a first physical address in the physical address space of that device, which first address is determined from said intermediate address, by a number of addresses ordered sequentially after said first address according to a predetermined order of physical addresses in the physical address space of that device, so as to obtain a final physical address corresponding to a non-defective location in that device, the number of addresses by which said first address is incremented being related to the number of defective memory locations prior to said first address, and any defective locations between said first and final physical addresses, according to said predetermined order, whereby different physical addresses may be applied to different devices when a data structure is written to or read from the different devices.

2. A memory system according to claim 1, wherein the controller is arranged to organise the memory locations in each memory device (42) into cells (50) so that if any cell contains a defective memory location then the entire cell is considered to be defective.

3. A memory system according to claim 1, wherein the controller (17) has a host address converter (21) for converting the host address to said intermediate address, a translator (22) for accessing the defect mapping means (46) and constructing said final physical address for a non-defective memory location for each device (42) using the intermediate address and where necessary the defect mapping means, and a data transfer unit (24) for applying the final physical addresses to the respective devices.

4. A memory system according to claim 3, wherein the translator (22) also determines the number of data structures which may be transferred in an uninterrupted sequence.

5. A memory system according to claim 1, wherein the defect mapping means (46) is in the form of a non-volatile memory.

6. A memory system according to claim 5, wherein the defect mapping means (46) comprises a programmable read-only memory (PROM).

7. A memory system according to claim 5, wherein the defect mapping means (46) for each device having a defective location is located on a single FLASH EPROM.

8. A memory system according to claim 2, wherein the defect mapping means (46) has an entry for each cell in each of the memory devices.

9. A memory system according to claim 1, wherein the memory devices are DRAM devices (42).

10. A memory system according to claim 1, wherein said predetermined order of physical addresses comprises the physical addresses ordered sequentially according to increasing physical address, from the lowest physical address to the highest physical address.

11. A controller (17) for use with a memory system (10) having a plurality of memory devices (42), at least one of the devices having a defective memory location, and the system having defect mapping means (46) associated with each memory device having a defective location, where the system is arranged and configured so that each data structure is divided into portions which are respectively stored in different memory devices, the controller (17) being arranged for converting the host address to an intermediate address for use in accessing a memory location in each of a plurality of said devices, accessing the defect mapping means using said intermediate address and thereby generating on a per device basis, for each device of said plurality of devices, a physical address corresponding to a non-defective location within that device by incrementing a first physical address in the physical address space of that device, which first physical is determined from said intermediate address, by a number of addresses ordered sequentially after said first address according to a predetermined order of physical addresses in the physical address space of that device, so as to obtain a final physical address corresponding to a non-defective location in that device, the number of addresses by which said first address is incremented being related to the number of defective memory locations prior to said first address, and any defective locations between said first and final physical addresses, according to said predetermined order, whereby different physical addresses may be applied to different devices when a data structure is written to or read from the different devices.

12. A method of storing and retrieving data structures, where the data structures are divided into portions which are respectively stored in different memory devices (42);

the method comprising the steps of;

providing a plurality of memory devices (42), where at least one of the memory devices has a defective memory location;

providing defect mapping means (46) associated with each memory device having a defective location;

on a per device basis, determining with reference to any defect mapping means (46) associated with that device (42) an address of a non-defective memory location within that device by converting the host address to an intermediate address for use in accessing a memory location in each of a plurality of said devices, accessing the defect mapping means using said intermediate address and thereby generating on a per device basis, for each device of said plurality of devices, a physical address corresponding to a non-defective location within that device by incrementing a first physical address in the physical address space of that device, which first physical is determined from said intermediate address, by a number of physical addresses ordered sequentially after said first address according to a predetermined order of physical addresses in the physical address space of that device, so as to obtain a final physical address corresponding to a non-defective location in that device, the number of addresses by which said first address is incremented being related to the number of defective memory locations prior to said first address, and any defective locations between said first and final physical addresses, according to said predetermined order;

applying the respective determined final physical addresses to the devices; and

one of reading a data structure from and writing a data structure to the respective memory locations accessed by the respective determined final physical addresses.