10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports

• US 6,285,726 B1
• Filed: 05/18/1998
• Issued: 09/04/2001
• Est. Priority Date: 05/18/1998
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Gaudet, Brian
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US09/080,740
• Time in Patent Office: 1,205 Days
• Field of Search: 375/327, 375/354, 375/355, 375/371, 375/373, 375/376, 375/361, 713/400, 713/401, 713/500, 713/501, 713/503, 713/600, 327/146, 327/147, 327/148, 327/149, 327/150, 327/152, 327/155, 327/159, 327/156, 327/157, 327/158, 327/163
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A clock recovery architecture for recovering clock and serial data from an incoming data stream of a local area network station. A phase picker architecture augmented by a phase interpolator is used as part of the clock recovery architecture to enhance phase resolution. A single clock generation module (CGM) and N phase multiplexers, one for each clock recovery channel on a chip, is used to select one of M phases of a 250 Mhz clock signal from the CGM for each clock recovery channel. To provide the required phase resolution, a phase interpolator is used. The phase interpolator is used to create a number of delay steps evenly spaced between the gross phase steps of the phase multiplexer. Each phase multiplexer is advanced or retarded in response to the pump-up (pumpup) or pump-down (pumpdn) signals from each clock recovery channel (CRM).

Claims

1. A clock recovery circuit comprising

a first phase comparator that detects a phase difference between a reference clock signal and a first input data signal, wherein the first phase comparator outputs a first lead pulse when the reference clock signal leads the first input data signal and outputs a first lag pulse when the reference clock signal lags the first input data signal;

a second phase comparator that detects a phase difference between the reference clock signal and a second input data signal, wherein the second phase comparator outputs a second lead pulse when the reference clock signal leads the second input data signal and outputs a second lag pulse when the reference clock signal lags the second input data signal;

a first pulse generator that responds to first lead pulses and to first lag pulses by providing a first pumpup/pumpdown output signal that includes pumpup pulses that correspond to each first lead pulse and pumpdown pulses that correspond to each first lag pulse;

a second pulse generator that responds to second lead pulses and to second lag pulses by providing a second pumpup/pumpdown output signal that includes pumpup pulses that correspond to each second lead pulse and pumpdown pulses that correspond to each second lag pulse;

a first pulse combiner that logically ORs the first pumpup/pumpdown output signal and the second pumpup/pumpdown output signal to provide a combined pumpup/pumpdown output signal;

a first pulse stream attenuator that masks out every N pulses from the combined pumpup/pumpdown output signal to provide a proportional control attenuator pulse signal, where N is an integer that provides a predefined amount of proportional control;

a second pulse stream attenuator that masks out every M pulses from the combined pumpup/pumpdown output signal to provide an integral control attenuator pulse signal, where M is an integer that provides a predefined amount of integral control;

an integrator that integrates the integral control attenuation pulse signal to provide an integrated up/down pulse signal; and

a second pulse combiner that combines the proportional control attenuation pulse signal and the integrated up/down pulse signal to provide an up/down output pulse stream having a pulse density proportional to the phase error and attenuated by proportional gain and by past history of the phase error.

2. The clock recovery circuit of claim 1, and wherein the integrator comprises an up/down counter.

3. The clock recovery circuit of claim 1, and further comprising:

a delay selector that outputs delay information in response to the up/down output pulse stream;

a clock source that generates a plurality of phase-separated base clock signals and provides a selected one of the phase-separated base clock signals as an output base clock signal based upon the delay information; and

a delay interpolator that delays the output base clock signal an amount based upon the delay information, the delayed output base clock signal corresponding to the reference clock signal.

4. The clock recovery circuit of claim 3, and wherein the delay information comprises an n-bit word capable of having a plurality of values, including a first value and a second value, the n-bit word changing its value in response to the up/down output pulse stream.

5. The clock recovery circuit of claim 4, and wherein the delay selector changes the delay information in response to the plurality of values.

6. The clock recovery circuit of claim 5, and wherein the clock source changes the selected one of the phase-separated base clock signals when the n-bit word changes from the first value to the second value, and when the n-bit word changes from the second value to the first value.

7.The clock recovery circuit of claim 5, and further comprising a divide-by-M circuit that divides down the delayed output base clock signal to provide the reference clock signal.

7. The clock recovery circuit of claim 4, and wherein the n-bit word includes a single logic one and a plurality of logic zeros, and wherein the single logic one is shifted in a first direction in response to each up pulse in the up/down output pulse stream, and wherein the single logic one is shifted in a second direction in response to each down pulse in the up/down output pulse stream.

8. The clock recovery circuit of claim 3 and further comprising:

a divide-by-S circuit that divides down the delayed output base clock signal to output a divided clock signal;

a third phase comparator connected to the delay block and the divide-by-S circuit that captures a third data signal with the delayed output base clock signal and the divided clock signal to form captured data, and determines mid-bit transition information from the captured data to output lead error information and lag error information;

a second filter connected to the divide-by-S circuit and the third phase comparator that filters the lead error information to output a second filtered up pulse stream, the second filtered up pulse stream having a pulse density proportional to a phase error between the delayed clock signal and the third data signal, and filters the lag error information to output a second filtered down pulse stream, the second filtered down pulse stream having a pulse density proportional to a phase error between the delayed clock signal and the third data signal; and

a multiplexer that passes the first filtered up pulse signal and the first filtered down pulse signal when data that defines the first and second data signals are to be recovered, and that passes the second filtered up pulse signal and the second filtered down pulse signal when data that defines the third data signal are to be recovered,

the delay selector outputting delay information in response to the first filtered up pulse stream and the first filtered down pulse stream when data that defines the first and second data signals are to be recovered, and outputting delay information in response to the second filtered up pulse stream and the second filtered down pulse stream when data that defines the third data signal are to be recovered.

9. The clock recovery circuit of claim 9, and wherein the third phase comparator comprises:

a shift register that receives the third data signal, shifts data through the register in response to edges of the delayed clock signal, and outputs parallel data held in the shift register in response to edges of the divided clock signal;

a latch connected to the shift register that holds the parallel data; and

a phase comparer connected to the latch that determines mid-bit transition information from the parallel data to output the lead error information and the lag error information.

10. The clock recovery circuit of claim 10, and wherein the divide-by-S circuit includes a reset circuit, the reset circuit outputting a reset signal that resets the divide-by-S circuit, the reset signal being output when a transition is detected after a predefined transition has not been detected for a predetermined period of time.