System and method for on-chip filter tuning

• US 6,285,865 B1
• Filed: 11/12/1999
• Issued: 09/04/2001
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Bult, Klaas, Carr, Frank
• Primary Examiner(s): Maung, Nay
• Assistant Examiner(s): Vuong, Quochien B.
• Application Number:
  US09/438,234
• Time in Patent Office: 662 Days
• Field of Search: 455/307, 455/280, 455/193.1, 455/150.1, 333/167, 333/172, 327/552, 327/554, 327/555
• US Class Current: 455/307
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. An integrated circuit chip comprising:

a first adjustable on-chip filter having a first plurality of selectable capacitors that determine its center frequency;

a second adjustable on-chip filter having a second plurality of selectable capacitors that determine its center frequency;

means for selecting a number of the first plurality of capacitors to adjust the first filter to a desired center frequency; and

means for transferring the selection of the first plurality of capacitors to the second plurality of capacitors to adjust the second filter to a center frequency proportional to the desired frequency.

2. The integrated circuit of claim 1, in which the transferring means adjusts the second filter to a center frequency that is equal to the desired frequency.

3. The integrated circuit of claim 1, in which the transferring means includes frequency scaling means that adjusts the second filter to a center frequency that is a multiple of the desired frequency.

4. The integrated circuit of claim 1, in which the multiple is a whole number.

5. The integrated circuit of claim 1, in which the multiple is a fraction.

6. The integrated circuit of claim 1, in which the transferring means operates after the number of first capacitors is selected.

7. The integrated circuit of claim 1, in which the first plurality of capacitors is selectable by switching the individual capacitors on and off and the selecting means comprises:

a local oscillator (LO);

means for coupling the LO to the first filter;

means for comparing the output of the LO to the output of the first filter; and

means for switching combinations of the first plurality of capacitors on and off until the outputs of the LO and the first filter have the same center frequency.

8. The integrated circuit of claim 7, in which the first plurality of capacitors are switched off after the selection of the first plurality of capacitors is transferred to the second plurality of capacitors.

9. The integrated circuit of claim 7, in which the switching means switches on and off combinations of the first plurality of capacitors such that the center frequency of the first filter is changed sequentially until the outputs of the LO and the first filter have the same center frequency.

10. An integrated circuit tuner comprising:

an on-chip crystal having a reference frequency;

means for generating a first oscillator output at the reference frequency;

a first adjustable on-chip filter having a first plurality of selectable capacitors that determine its center frequency;

a second adjustable on-chip filter having a second plurality of selectable capacitors that determine its center frequency;

means for selecting a number of the first plurality of capacitors to adjust the first filter to the reference frequency; and

means for transferring the selection of the first plurality of capacitors to the second plurality of capacitors to adjust the second filter to a frequency proportional to the reference frequency.

11. A method for on-chip filter tuning comprising:

stimulating a dummy filter with a frequency available in the receiver by utilizing the frequency as the filter stimulus;

tuning the dummy filter to its designed center frequency by switching in capacitors to shift the filter response curve down in frequency;

calculating the capacitor values required to center the response of the actual filter to its designed center frequency;

adding the calculated capacitance to the actual filter so that its response curve is centered about its designed center frequency; and

removing the tuning circuitry from the signal path.

13. The electronic tuning circuitry for tuning a filter of claim 11 further comprising a low pass filter cascaded between the phase detector output and comparator input.

14. The electronic tuning circuitry for tuning a filter of claim 11 further comprising a second phase detector connected in parallel with the first phase detector.

15. The electronic tuning circuitry for tuning a filter of claim 14 in which the second phase detector I and Q inputs are connected to the first phase detector Q and I inputs respectively.

12. Electronic tuning circuitry for tuning a filter comprising:

a first switchable capacitor that is part of a tunable filter that is capable of being tuned to a first characteristic frequency;

a dummy filter capable of being tuned to a second characteristic frequency;

a second switchable capacitor that is part of the tunable dummy filter;

a signal generator producing the second characteristic frequency and applying it to the dummy filter;

a first phase detector that compares the phase of the dummy filter input to the dummy filter output;

a comparator that produces an output signal indicative of the dummy filter being tuned to the second characteristic frequency; and

a counter that continues to switch in first and second switchable capacitors simultaneously until disabled by the comparator circuit.

16. The electronic tuning circuitry for tuning a filter of claim 12 in which the circuitry described is configured differentially.

17. The electronic tuning circuitry for tuning a filter of claim 12 in which the first switchable capacitor is selected such that its value is scaled in frequency to the value of the second switchable capacitor to produce the desired tuning response in the filter.

18. Electronic tuning circuitry for tuning a filter comprising:

a dummy filter means for producing a tuned response at a frequency of a locally available frequency generator;

a filter means for filtering unwanted signals from a desired signal;

a phase detector means for detecting a phase difference across a set of dummy filter terminals with minimal DC off set;

a low pass filter means for removing AC signals from the phase detector output;

a comparator means for indicating that a desired phase difference has been achieved; and

a counter means for tuning a filter until disabled by the comparator means.

19. Electronic tuning circuitry for tuning a filter comprising:

a substrate upon which the electronic tuning circuitry is disposed;

a first switchable capacitor that is part of a tunable filter that is capable of being tuned to a first characteristic frequency;

a dummy filter capable of being tuned to a second characteristic frequency;

a second switchable capacitor that is part of the tunable dummy filter;

a signal generator producing the second characteristic frequency and applying it to the dummy filter;

a first phase detector that compares the phase of the dummy filter input to the dummy filter output;

a comparator that produces an output signal indicative of the dummy filter being tuned to the second characteristic frequency; and

a counter that continues to switch in first and second switchable capacitors simultaneously until disabled by the comparator circuit.

20. The electronic tuning circuitry for tuning a filter of claim 19 wherein the substrate is silicon.

21. The electronic tuning circuitry for tuning a filter of claim 19 further comprising a low pass filter cascaded between the phase detector output and comparator input.

22. The electronic tuning circuitry for tuning a filter of claim 19 further comprising a second phase detector connected in parallel with the first phase detector.

23. The electronic tuning circuitry for tuning a filter of claim 22 in which the second phase detector I and Q inputs are connected to the first phase detector Q and I inputs respectively.

24. The electronic tuning circuitry for tuning a filter of claim 19 in which the circuitry described is configured differentially.

25. The electronic tuning circuitry for tuning a filter of claim 19 in which the first switchable capacitor is selected such that its value is scaled in frequency to the value of the second switchable capacitor to produce the desired tuning response in the filter.