Microcomputer having a built-in A/D converter with a resistor between an external terminal and an I/O circuit

• US 6,286,065 B1
• Filed: 11/18/1998
• Issued: 09/04/2001
• Est. Priority Date: 11/18/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Suzuki, Hideyuki
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/193,847
• Time in Patent Office: 1,021 Days
• Field of Search: 710/65-71, 341/144-158
• US Class Current: 710/69
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)

Abstract

The present invention provides a microcomputer having a built-in A/D converter circuit and sharing an external terminal with an input terminal of the A/D converter so as to reduce the size and weight of the semiconductor integrated circuit, wherein a resistor is inserted to eliminate deterioration of the A/D converter circuit due to the reduction in the number of the terminals.

Claims

1. A microcomputer comprising:

an internal circuit having a data processing function;

a built-in A/D converter circuit connected to said internal circuit;

an I/O circuit connected to said internal circuit;

an external terminal for input/output shared by an input terminal of said A/D converter circuit;

a first branch wire connecting said external terminal via said I/O circuit to said internal circuit;

a second branch wire connecting said external terminal to said A/D converter circuit, and

a predetermined resistor inserted on said first branch wire connecting said external terminal to said I/O circuit and designed to have a sufficiently higher resistance than a parasitic resistance of said first branch wire.

2. A microcomputer as claimed in claim 1, said microcomputer further comprising a main wire provided between said external terminal and a branching point of said first branch wire and said second branch wire.

3. A microcomputer as claimed in claim 1, wherein said I/O circuit includes:

a first-conductive field effect transistor (FET) having a source connected to a high-potential power source, a gate supplied with a first control signal from said internal circuit, and a drain connected to a terminal of said predetermined resistor;

a second-conductive field effect transistor (FET) having a drain connected to said drain of said first-conductive FET, a gate supplied with a second control signal from said internal circuit, and a source connected to a low-potential power source; and

a NAND circuit having a first input terminal connected to said terminal of said predetermined resistor, a second input terminal supplied with an input control signal from said internal circuit, and an output terminal connected to said internal circuit.

4. A microcomputer as claimed in claim 2, wherein said I/O circuit includes:

a first-conductive field effect transistor (FET) having a source connected to a high-potential power source, a gate supplied with a first control signal from said internal circuit, and a drain connected to a terminal of said predetermined resistor;

a second-conductive field effect transistor (FET) having a drain connected to said drain of said first-conductive FET, a gate supplied with a second control signal from said internal circuit, and a source connected to a low-potential power source; and

a NAND circuit having a first input terminal connected to said terminal of said predetermined resistor, a second input terminal supplied with an input control signal from said internal circuit, and an output terminal connected to said internal circuit.

5. The microcomputer according to claim 1, wherein the predetermined resistor is designed to have a resistance value at least one hundred times the parasitic resistance of the first branch wire.

6. The microcomputer according to claim 2, wherein the predetermined resistor is designed to have a resistance value at least one hundred times the parasitic resistance of the first branch wire.