Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein

• US 6,286,126 B1
• Filed: 04/13/1999
• Issued: 09/04/2001
• Est. Priority Date: 08/30/1996
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Avant! Corporation (Synopsys Incorporated)
• Inventors: Raghavan, Vivek, Zimmerman, Brian A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/292,783
• Time in Patent Office: 875 Days
• Field of Search: 716/1-21
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets. The delay estimates are then used to determine a net timing error bound associated with each net. These net timing error bounds are then filtered against a user-specified net timing error tolerance to determine which nets have an excessive timing error bound. Those nets having excessive timing error bounds are then modeled using more accurate models.

Claims

1. A method of extracting nets interconnecting active devices in an integrated circuit, comprising the steps of:

extracting first estimates of the resistance of each of a first plurality of nets in the integrated circuit;

extracting first estimates of the capacitance of each of the first plurality of nets in the integrated circuit;

determining for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net;

determining for each of the first plurality of nets, a respective minimum delay model that attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net;

determining based on the minimum and maximum delay models of each of the first plurality of nets, a second plurality of nets in the integrated circuit which require more accurate modeling; and

modeling each of the second plurality of nets as a respective distributed RC network.

2. A computer program product to extract nets interconnecting active devices in an integrated circuit, comprising a computer readable storage medium having computer-readable program code means embodied in said medium, said computer-readable program code means comprising:

computer-readable program code means for extracting first estimates of the resistance of each of a first plurality of nets in the integrated circuit;

computer-readable program code means for extracting first estimates of the capacitance of each of the first plurality of nets in the integrated circuit;

computer-readable program code means for determining for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net;

computer-readable program code means for determining for each of the first plurality of nets, a respective minimum delay model that attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net;

computer-readable program code means for determining based on the minimum and maximum delay models of each of the first plurality of nets, a second plurality of nets in the integrated circuit which require more accurate modeling; and

computer-readable program code means for modeling each of the second plurality of nets as a respective distributed RC network.

3. An apparatus to extract nets interconnecting active devices in an integrated circuit, comprising:

means for extracting first estimates of the resistance of each of a first plurality of nets in the integrated circuit;

means for extracting first estimates of the capacitance of each of the first plurality of nets in the integrated circuit;

means for determining for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net;

means for determining for each of the first plurality of nets, a respective minimum delay model that attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net;

means for determining based on the minimum and maximum delay models of each of the first plurality of nets, a second plurality of nets in the integrated circuit which require more accurate modeling; and

means for modeling each of the second plurality of nets as a respective distributed RC network.