Multi-chip semiconductor chip module

• US 6,287,949 B1
• Filed: 09/01/1998
• Issued: 09/11/2001
• Est. Priority Date: 06/20/1994
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Mori, Syuji, Sekiba, Takasi, Kudo, Osamu
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US09/145,027
• Time in Patent Office: 1,106 Days
• Field of Search: 438/107, 438/109, 438/110, 438/112, 438/113, 438/114, 438/118, 438/124, 438/127, 438/462, 438/463, 438/612, 438/615, 438/617
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/1815 Shape
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Claims

1. A method for fabricating a semiconductor device, said semiconductor device including a plurality of chip units each including a semi conductor chip and a base member carrying thereon said plurality of chip units, comprising the steps of:

disposing said plurality of chip units on said base member such that the chip units that are disposed adjacent each other abut with each other at respective side edges in a flush manner with no spaces between said chip units, thereby establishing interconnection of terminals provided on a chip unit with corresponding terminals provided on an adjacent chip unit, said plurality of chip units forming thereby a multi-chip assembly; and

providing an interconnection with a terminal on said multi-chip assembly and a corresponding interconnection pad provided on said base member.

2. A method as claimed in claim 1, wherein said step of providing an interconnection includes a step of causing a fusion in said terminal on said multi-chip assembly upon said interconnection pad, said step of fusion thereby providing a mechanical connection of said multi-chip assembly upon said base member.

3. A method for fabricating a semiconductor device, said semiconductor device including a plurality of chip units each including a semiconductor chip and a base member carrying thereon said plurality of chip units, comprising the steps of:

disposing said plurality of chip units on said base member such that the chip units that are disposed adjacent each other abut with each other at respective side edges in a flush manner, thereby establishing interconnection of terminals provided on a chip unit with corresponding terminals provided on an adjacent chip unit, said plurality of chip units forming thereby a multi-chip assembly; and

providing an interconnection with a terminal on said multi-chip assembly and a corresponding interconnection pad provided on said base member,

wherein said step of providing an interconnection includes a step of causing a fusion in said terminal on said multi-chip assembly upon said interconnection pad, said step of fusion thereby providing a mechanical connection of said multi-chip assembly upon said base member, and

wherein said interconnection pad on said base member includes a conductive sleeve provided in a through hole formed on said base member, and wherein said step of causing the fusion in said terminal includes a step of fusing said terminal of said multi-chip assembly by means of a laser beam irradiated thereupon through said conductive sleeve.

4. A method for fabricating a semiconductor device, comprising the steps of:

forming depressions on a wafer in which a plurality of integrated circuit patterns are formed, such that each of said depressions is formed in correspondence to a terminal region of an integrated circuit pattern;

filling said depressions by a conductive member to form terminals;

scribing said wafer into a plurality of chip units each carrying an integrated circuit pattern; and

assembling the plurality of said chip units adjacent each other such that each chip unit has a side edge engaging with a corresponding side edge of an adjacent chip unit, to form a multi-chip module.

5. A method as claimed in claim 4, wherein said step of assembling includes a step of disposing said plurality of chip units upon a base member.

6. A method as claimed in claim 4, wherein said step of forming depressions includes a step of grooving a surface of said wafer by using one of a laser beam and a grinding blade.

7. A method as claimed in claim 5, further comprising a step of mending one or both of said integrated circuit patterns and said terminals on said chip units by means of either of a laser beam and a grinding blade, at one of the stages of:

before forming said depressions;

forming said depressions;

after arranging said chip units; and

after mounting said chip units upon said base member.