Process for forming a combination hardmask and antireflective layer

• US 6,287,951 B1
• Filed: 12/07/1998
• Issued: 09/11/2001
• Est. Priority Date: 12/07/1998
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lii, Yeong Jyh, Clark, Wayne D., Pettinato, Christopher D., Filipiak, Stanley M., Lucas, Kevin D.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US09/206,715
• Time in Patent Office: 1,009 Days
• Field of Search: 438/597, 438/618, 438/622, 438/631, 438/633, 438/636, 438/637, 438/706, 438/707, 438/710, 438/735, 438/737, 438/738
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A hardmask layer (34) is formed over insulating layers (26, 24, 22 and 20), and an antireflective layer (36) is formed overlying the hardmask layer (34). A resist layer (38) is formed overlying the antireflective layer (36), and an opening is formed in the resist layer to expose a surface portion of the antireflective layer (36). The exposed surface portion of the antireflective layer (36) and portions of the hardmask layer (34) are etched to expose a surface portion of the insulating layers (26, 24, 22 and 20), and a feature opening (61) is formed in the insulating layers (26, 24, 22 and 20). A conductive material (74) is deposited to fill the feature opening (61), and portions of the conductive material (74) lying outside the opening are removed.

Claims

1. A process for forming a semiconductor device comprising:

forming an insulating layer over a semiconductor device substrate;

forming an adhesion layer comprising silicon over the insulating layer, wherein the adhesion layer has a thickness in a range of 3-8 nanometers;

forming a silicon hardmask layer over the adhesion layer;

forming a silicon oxynitride antireflective layer overlying the silicon hardmask layer;

forming a resist layer overlying the silicon oxynitride antireflective layer;

forming an opening in the resist layer to form an exposed surface portion of the silicon oxynitride antireflective layer;

etching the exposed surface portion of the silicon oxynitride antireflective layer and a portion of the silicon hardmask layer to form an exposed surface portion of the insulating layer; and

etching the exposed surface portion of the insulating layer to form a feature opening in the insulating layer.

2. The process of claim 1, wherein the adhesion layer comprises silicon nitride.

3. The process of claim 1, wherein the silicon hardmask layer has a thickness in a range of approximately 15-45 nanometers.

4. The process of claim 1, wherein the silicon oxynitride antireflective layer has a thickness in a range of approximately 15-45 nanometers.

5. The process of claim 1, wherein the adhesion layer has an intrinsic stress between 120 Mega Pascals compressive and 120 Mega Pascals tensile.

6. The process of claim 1, wherein forming the silicon hardmask layer and forming the silicon oxynitride antireflective layer are performed in a same plasma enhanced chemical vapor deposition system during a single deposition processing sequence.

7. The process of claim 1, further comprising removing the resist layer after etching the exposed surface portion of the silicon oxynitride antireflective layer and before etching the exposed surface portion of the insulating layer.

8. The process of claim 1, wherein etching the exposed surface portion of the silicon oxynitride antireflective layer and etching the exposed surface portion of the insulating layer are performed in a same etch chamber during a single etch processing sequence.

9. The process of claim 8, further comprising removing the resist layer after etching the exposed surface portion of the silicon oxynitride antireflective layer and before etching the exposed surface portion of the insulating layer.

10. The process of claim 1, further comprising:

depositing a conductive material over the semiconductor device substrate to fill the feature opening; and

removing portions of the conductive material.

11. The process of claim 10, wherein removing portions of the conductive material also removes portions of the silicon hardmask layer.

12. A process for forming a semiconductor device comprising:

forming an insulating layer over a semiconductor device substrate;

forming an adhesion layer comprising silicon over the insulating layer, wherein the adhesion layer has a thickness in a range of 38 nanometers;

forming a silicon hardmask layer over the insulating layer, wherein the silicon hardmask layer has a thickness in a range of approximately 15-45 nanometers;

forming a silicon oxynitride antireflective layer overlying the silicon hardmask layer wherein the silicon oxynitride antireflective layer has a thickness in a range of approximately 15-45 nanometers;

forming a resist layer overlying the silicon oxynitride antireflective layer;

forming an opening in the resist layer to form an exposed surface portion of the silicon oxynitride antireflective layer;

etching the exposed surface portion of the silicon oxynitride antireflective layer and a portion of the silicon hardmask layer to form an exposed surface portion of the insulating layer;

etching the exposed surface portion of the insulating layer to form an interconnect opening in the insulating layer; and

forming an interconnect within the interconnect opening.

13. The process of claim 12, wherein the adhesion layer comprises silicon nitride.

14. The process of claim 12, wherein the adhesion layer has an intrinsic stress between 120 Mega Pascals compressive and 120 Mega Pascals tensile.

15. A process for forming a semiconductor device comprising:

forming an insulating layer over a semiconductor device substrate;

forming an adhesion layer comprising silicon over the insulating layer;

forming a silicon hardmask layer over the adhesion layer;

forming a plasma enhanced nitride antireflective layer overlying the silicon hardmask layer, wherein forming the adhesion layer, the silicon hardmask layer, and the nitride antireflective layer are performed in a same plasma enhanced chemical vapor deposition chamber during a single deposition processing sequence;

forming a resist layer overlying the nitride antireflective layer;

forming an opening in the resist layer to form a first exposed surface portion of the nitride antireflective layer;

etching the first exposed surface portion of the nitride antireflective layer, portions of the silicon hardmask layer, and portions of the adhesion layer to form an exposed surface portion of the insulating layer;

removing the resist layer;

etching the exposed surface portion of the insulating layer and a second exposed surface of the nitride antireflective layer to form an opening in the insulating layer and remove portions of the second exposed surface of the nitride antireflective layer;

depositing a conductive material over the semiconductor device substrate to fill the opening; and

removing the silicon hardmask layer, the adhesion layer, and portions of the conductive material lying outside the opening.

16. The process of claim 15, wherein the adhesion layer comprises silcon nitride.

17. The process of claim 15, wherein the silicon hardmask layer has a thickness in a range of approximately 15-45 nanometers.

18. The process of claim 15, wherein the nitride antireflective layer has a thickness in a range of approximately 15-45 nanometers.

19. The process of claim 15, wherein the adhesion layer has an intrinsic stress between 120 Mega Pascals compressive and 120 Mega Pascals tensile.

20. The process of claim 15, wherein etching the first exposed surface portion of the nitride antireflective layer, removing the resist layer, and etching the exposed surface portion of the insulating layer are all performed in a same processing chamber during a single processing sequence.