Integrated EMI shield utilizing a hybrid edge

• US 6,288,344 B1
• Filed: 08/20/1999
• Issued: 09/11/2001
• Est. Priority Date: 08/20/1999
• Status: Expired due to Term

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Youker, Nick A., Blood, James E., Hansen, John E.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): PATEL, ISHWARBHAI B
• Application Number:
  US09/378,407
• Time in Patent Office: 753 Days
• Field of Search: 174/250, 174/255, 174/256, 174/254, 174/258, 174/36, 174/251, 174/260, 361/783, 361/760, 361/792, 361/793, 361/794, 361/795, 361/799, 361/800, 257/707, 257/692, 257/779, 257/778, 257/736
• US Class Current: 174/255
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15156 Side view
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H05K 9/0039 Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing printed shielding conductors, ground planes or power planes for reduction of cross-talk or noise in printed circuits H05K1/0218
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

The present embodiments and associated methods provide for an integrated EMI shield for effective shielding not only from emissions perpendicular to the integrated circuit (IC) chip carrier but also parallel (edgewise) to the carrier. In one embodiment, an IC chip carrier comprises an insulating ceramic substrate and at least one internal electrically conductive layer being a circuit ground, portions of which extend to the edge of the substrate, the internal electrically conductive layer in electrical contact with an electrically conductive layer applied to a portion of the substrate edge. This provides a horizontal hybrid ground plane which can be used as an EMI shield that runs horizontally to the chip as well as a hybrid edge EMI shield perpendicular along at least a portion of the edge. This edge shield protects internal circuitry from exterior EMI emissions directed towards the chip carrier edge portion incorporating the shield.

Claims

1. An integrated circuit chip carrier, comprising:

an electrically insulating substrate having an edge, a first side, a second side, at least one conduction path, and one or more cavities extending from the first side, the one or more cavities adapted to at least substantially enclose one or more electrical components, the one or more cavities further comprising at least one bond pad in electrical communication with the at least one conduction path, the at least one bond pad adapted to electrically communicate with the one or more electrical components;

at least one internal electrically conductive layer adapted to be a circuit ground, at least a portion of the at least one internal electrically conductive layer extending to the edge of the substrate; and

a second electrically conductive layer on at least a portion of the substrate edge, the at least one internal electrically conductive layer in electrical contact with the second electrically conductive layer.

2. An integrated circuit chip carrier according to claim 1, wherein the substrate is a ceramic material.

3. An integrated circuit chip carrier according to claim 2, wherein the second electrically conductive layer is tungsten.

4. An integrated circuit chip carrier according to claim 2, wherein the second electrically conductive layer is molybdenum.

5. The chip carrier as recited in claim 1, the one or more cavities further comprising a plurality of walls, a bottom, and one or more levels defined by steps in the cavity walls.

6. The chip carrier as recited in claim 5, the one or more steps further comprising at least one bond pad in electrical communication with the at least one conduction path.

7. The chip carrier as recited in claim 6, wherein the at least one bond pad is adapted to electrically connect with a corresponding integrated circuit chip bond pad.

8. The chip carrier as recited in claim 1, further comprising one or more first side bond pads disposed on the first side, the one or more first side bond pads adapted to electrically connect with electrical component bond pads, the one or more first side bond pads adapted to electrically connect with at least one of the at least one conduction paths.

9. The chip carrier as recited in claim 1, wherein the at least one conduction path extends to the second side and is adapted to electrically communicate with an external device.

10. The chip carrier as recited in claim 1, wherein the at least one conduction path extends to the first side or the second side and is adapted to electrically communicate with an external device.

11. The chip carrier as recited in claim 1, wherein the one or more cavities completely enclose the one or more electrical components.

12. The chip carrier as recited in claim 1, wherein at least one of the one or more electrical components is an integrated circuit chip.

13. The chip carrier as recited in claim 1, wherein the substrate further comprises a plurality of layers, each layer comprising a substantially planar sheet of insulating material upon which and through which one or more conduction paths are desposed, one or more layers further comprising one or more voids, wherein the plurality of layers are adapted to be stacked and consolidated to form the substrate, the voids forming the one or more cavities, and the one or more conduction paths forming interconnecting conduction paths with the at least one bond paths.

14. The chip carrier as recited in claim 1, the one or more cavities further comprising a bottom surface and a side surface, wherein the at least one internally conductive layer substantially prevents electromagnetic emissions from passing through the bottom of at least one of the one or more cavities, and wherein the second electrically conductive layer substantially prevents electromagnetic emissions from passing through the side of at least one of the one or more cavities.

15. A circuit board comprising:

a substrate having an edge, a top surface and a bottom surface, at least one conduction path, and one or more cavities extending from the top surface, the one or more cavities adapted to at least substantially enclose one or more electrical components, the cavities further comprising one or more bond pads to electrically connect the one or more electrical components to the at least one conduction path, the substrate comprising a thermoplastic polymeric material;

one or more electrical components disposed substantially within the one or more cavities;

an electrically grounded planar conductive layer substantially encapsulated by the substrate, the planar conductive layer adapted to shield the electrical components from electromagnetic interference originating from a side of the planar conductive layer opposite from the electrical components;

a least a portion of the planar conductive layer extending outward to the edge of the substrate; and

an edge conductive layer on at least a portion of the edge of the substrate, wherein the edge conductive layer is electrically connected to the planar conductive layer, the edge conductive layer adapted to substantially block electromagnetic interference emissions originating from a side of the edge conductive layer opposite from the electrical components.

16. The circuit board as recited in claim 15, the one or more cavities further comprising a bottom surface and a side surface, wherein the at least one internally conductive layer substantially prevents electromagnetic emissions from passing through the bottom of at least one of the one or more cavities, and wherein the second electrically conductive layer substantially prevents electromagnetic emissions from passing through the side of at least one of the one or more cavities.

17. A shielded electric circuit board, comprising:

a planar substrate having a top and bottom surface, an edge, and one or more cavities extending from the top surface, the one or more cavities adapted to at least substantially enclose one or more electrical components, the one or more cavities further comprising one or more bond pads to electrically connect the one or more electrical components with the circuit board;

at least one conductive ground layer internal to the substrate, at least a portion of the ground layer extending outward to the substrate edge; and

an edge conductive layer on at least a portion of the substrate edge, the edge conductive layer electrically connected to the ground layer.

18. The shielded electric circuit board in accordance with claim 17, wherein the substrate includes at least one internal signal layer, said signal layer being co-planar with the internal ground layer and being electrically insulated from the ground layer and the external surfaces of said substrate.

19. The shielded electric circuit board as recited in claim 18, the one or more cavities further comprising a bottom surface and a side surface, wherein the at least one internally conductive layer substantially prevents electromagnetic emissions from passing through the bottom of at least one of the one or more cavities, and wherein the second electrically conductive layer substantially prevents electromagnetic emissions from passing through the side of at least one of the one or more cavities.