Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus

• US 6,288,561 B1
• Filed: 06/07/1995
• Issued: 09/11/2001
• Est. Priority Date: 05/16/1988
• Status: Expired due to Term

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US08/474,489
• Time in Patent Office: 2,288 Days
• Field of Search: 324/760, 324/757, 324/754, 324/755, 324/758, 324/765
• US Class Current: 324/750.07
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2867 Handlers or transport devices, e.g. loaders, carriers, trays
• CPC Class Codes: G01R 31/2868 Complete testing stations; systems; procedures; software aspects
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/67138 Apparatus for wiring semiconductor or solid state device
• CPC Class Codes: H01L 21/67706 Mechanical details, e.g. roller, belt H01L21/67709 takes precedence
• CPC Class Codes: H01L 21/67721 the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames H01L21/6773 takes precedence
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 : SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 : Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 : Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 22/22 : Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/7565 : Means for transporting the components to be connected
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 23/498 : Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/538 : the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 : Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A single gas tight system which performs multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having (1) a plurality of modules each having a holding fixture, a wafer, a probing device, an electronic circuit board, and a temperature control device, (2) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, (3) a handler for moving the wafers and the probing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures and the probing devices. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device. An integrated circuit has a plurality of conductive contact portions that are able to be connected to probe points of the probing device. A temperature control device is used to heat the wafer during an oxide reduction process or during burn-in of the wafer. During the oxide reduction process, hydrogen is introduced into the chamber, and the wafer is heated so that the oxides on the contact pads can combine with hydrogen to form water vapor, thus reducing the thickness of the oxides. The computer analyzes the test and/or burn-in data and provides control signals for repairing or programming the integrated circuits. The computer system also generates a database that contains the performance data of all the integrated circuits on the wafer that are tested and allows for immediate feedback of the quality of the integrated circuits.

Claims

1. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least one of functional testing, at-speed functional testing and burn-in processing, said integrated processing electronics being controlled by a programmed computer including a random access memory, said system comprising:

a first module having;

a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed; and

means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points;

wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.

2. The system according to claim 1, wherein at least one module of said first and second modules further comprises:

a temperature control device for modifying the temperature of at least one of said first and second substrates.

3. The system according to claim 1 wherein at least one said first and second modules further comprises:

a gas source for supplying at least a non-oxidizing gas into said at least one module.

4. The system according to claim 3 wherein, to reduce the thickness of the oxides on said plurality of conductive contact portions of said at least one substrate, said temperature control device modifies the temperature of said at least one substrate, and said gas source provides hydrogen over said oxides.

5. The system according to claim 1 comprising a handler for moving said first and second substrates.

6. The system according to claim 5 further comprising a computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device

wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:

(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;

(b) testing functionality of said integrated circuits of said at least one substrate;

(c) burning-in said at least one substrate;

(d) repairing said integrated circuits of said at least one substrate;

(e) programming said integrated circuits of said at least one substrate;

(f) marking a symbol on said at least one substrate; and

,

(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.

7. The system according to claim 1 wherein at least one of said modules comprises an electronic circuit board coupled to a computer.

8. The system according to claim 1 wherein said integrated circuits of said at least one substrate are functionally tested, burned-in and configured in said chamber.

9. The system according to claim 1 wherein said at least one module is gas tight.

10. The system according to claim 1 wherein said at least one substrate is a whole semiconductor wafer.

11. The system according to claim 10 farther including said computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device

wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:

(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;

(b) concurrently testing functionality of substantially all of said integrated circuits of said at least one substrate;

(c) concurrently burning-in substantially all of said integrated circuits of said at least one substrate;

(d) concurrently repairing substantially all of said integrated circuits of said at least one substrate;

(e) concurrently programming substantially all of said integrated circuits of said at least one substrate;

(f) marking a symbol on said at least one substrate; and

,

(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.

12. The system according to claim 1 further including a second temperature control device for modifying the temperature of said second substrate, wherein said first module and said second module perform same functions simultaneously.

13. The system of claim 1 further comprising said first probing device, wherein said first probing device includes integrated test electronics for performing both functional testing and burn-in testing of integrated circuits.

14. The system of claim 13, wherein said first probing device is a full-substrate probing device.

15. The system of claim 14, further comprising:

a second module having;

a second holding fixture, said holding fixture for holding a second substrate having integrated circuits, each of said integrated circuits having a plurality of conductive contact portions; and

means for coupling a computer to a second probing device of a type having integrated test electronics for performing testing of integrated circuits;

wherein said second module causes coupling of said plurality of conductive contact portions to probe points of said second probing device.

16. The system of claim 1, further comprising said first probing device, including a plurality of probe points for simultaneously contacting substantially all of the contact pads on an integrated circuit wafer;

wherein said integrated test electronics allow each circuit to be individually electrically tested.

17. The system according to claim 16 further comprising:

a gas source for supplying at least a first gas into said system; and

a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.

18. The system according to claim 17 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.

19. The system according to claim 17 wherein said system is a gas tight system.

20. The system according to claim 16 including a plurality of internal modules wherein:

a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer; and

a second one of said internal modules includes

a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,

means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested, and,

a second holding fixture for holding the second wafer.

21. The system according to claim 20 further including a handler for moving said first and second wafers and for moving said first and second probing devices;

wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;

wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and

wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.

22. The system according to claim 16 wherein said integral test electronics comprises integrated circuitry.

23. The system according to claim 22 wherein said integrated circuitry comprises active switching circuits.

24. The system according to claim 16 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.

25. The system according to claim 16 wherein the probing device comprises a membrane including said plurality of probe points.

26. The system according to claim 25 wherein said first control electronics comprises integrated circuitry in the first probing device.

27. The system according to claim 26 wherein said integrated circuitry comprises active switching circuits.

28. The system according to claim 25 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.

29. The system according to claim 25 further comprising:

a gas source for supplying at least a first gas into said system;

a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.

30. The system according to claim 29 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.

31. The system according to claim 29 wherein said system is a gas tight system.

32. The system according to claim 25 including a plurality of internal modules wherein

a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer;

and

a second one of said internal modules includes

a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,

means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested and,

a second holding fixture for holding the second wafer.

33. The system according to claim 32 further including a handler for moving said first and second wafers and for moving said first and second probing devices;

wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;

wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and

wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.

34. The system according to claim 33 wherein said probe points of said first probing device are in contact with said conductive contact portions of said integrated circuits of said first substrate for functional circuit testing, electrical burn-in, repair, or programming wherein

for said functional circuit testing, said computer sends first electrical signals to said first electronic circuit board, said first electronic circuit board sends second electrical signals to said circuits of said first probing device so that third electrical signals are applied to said conductive contact portions of said integrated circuits of said first substrate through said probe points of said first probing device, and fourth electrical signals produced in response to said third electrical signals are transmitted to said computer;

for said electrical burn-in, each of said integrated circuits of said first substrate is tested for a predetermined time period over a range of predetermined temperature and electrical conditions to produce burn-in data;

for said repair, said computer sends electrical signals causing an electrical stimulus to be applied via selected ones of said probe points to cause one of a fuse circuit device and an anti-fuse circuit device to change state; and

for said programming, said computer sends electrical signals causing electrical stimuli to be applied via selected ones of said probe points to cause binary values to be stored non-volatiley in said circuits.

35. The system according to claim 34 wherein

said computer analyzes data corresponding to said fourth electrical signals or said burn-in data and produces circuit repair or circuit programming signals wherein said first probing device performs circuit repair using said circuit repair signals or programs said integrated circuits of said first substrate through said probe points of said first probing device.

36. The system according to claim 35 wherein said computer generates a database from performance data corresponding to each of said integrated circuits of said first substrate for manufacturing control immediately after completion of substrate fabrication.

37. The apparatus of claim 1 further comprising said first probing device.

38. The apparatus of claim 37 wherein said integrated test electronics are passive only.

39. The apparatus of claim 1 wherein said integrated test electronics include active switching circuitry.

40. The apparatus of claim 39, wherein said active switching circuitry causes a given signal line to be coupled to a first probe point at a first time and a second different probe point at a second different time.

41. The apparatus of claim 40 wherein said first and second probe points each correspond to an output pad of an integrated circuit.

42. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least one of functional testing, at-speed functional testing and burn-in processing, said system comprising:

a first module having;

a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed;

a programmed computer including a random access memory for controlling said integrated processing electronics formed on said first full-substrate probing device and for causing electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device, wherein throughout processing of said first substrate each respective probe point is electrically coupled to conductive contacts of no more than a single respective integrated circuit; and

means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points.

43. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, integrated circuits to be processed including substantially all said integrated circuits, from a first integrated circuit on said first substrate to be processed to a last integrated circuit on said first substrate to be processed, said integrated circuits having a plurality of conductive contact portions, said system comprising:

a first module having;

a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed;

a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuit die formed on said first substrate, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least one of functional testing, at-speed functional testing and burn-in processing;

a programmed computer including a random access memory for controlling said integrated processing electronics formed on said first full-substrate probing device and for causing electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device, wherein throughout processing of said first substrate each respective probe point is electrically coupled to conductive contacts of no more than a single respective integrated circuit; and

means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points.

44. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least two different functions selected from the group consisting of functional testing, at-speed functional testing, burn-in, programming and repair processing, said integrated processing electronics being controlled by a programmed computer including a random access memory, said system comprising:

a first module having;

a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed; and

means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics than said first full-substrate probing device has probe points, signals carried by said signal lines including control signals controlling the type of processing to be performed;

wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.

45. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for performing at least one of functional testing, at-speed functional testing and burn-in processing, said integrated processing electronics being controlled by a programmed computer including a random access memory, said system comprising:

a first module having;

a first holding fixture for holding said first substrate, including a thermal control unit for controlling temperature of the first substrate, wherein maximum travel, in a plane of said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed;

a controlled-atmosphere chamber surrounding said holding fixture and including a gas source for, in cooperation with said thermal control unit, creating an atmosphere for reducing oxides on said conductive contact portions; and

means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points;

wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.

46. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for performing at least one of functional testing, at-speed functional testing and bum-in processing, said integrated processing electronics being controlled by a general-purpose programmed computer including a random access memory, said system comprising:

a first module having;

a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed; and

means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points;

wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.

47. The system of claim 46 further comprising said first probing device, wherein said first probing device includes integrated test electronics for performing both functional testing and burn-in testing of integrated circuits.

48. The system of claim 47, further comprising:

a second module having;

a second holding fixture, said holding fixture for holding a second substrate having integrated circuits, each of said integrated circuits having a plurality of conductive contact portions; and

means for coupling a computer to a second probing device of a type having integrated test electronics for performing testing of integrated circuits;

wherein said second module causes coupling of said plurality of conductive contact portions to probe points of said second probing device.

49. The system of claim 46, wherein said first probing device is a full-substrate probing device.

50. The system according to claim 49, wherein at least one module of said first and second modules further comprises:

a temperature control device for modifying the temperature of at least one of said first and second substrates.

51. The system according to claim 49 wherein, to reduce the thickness of the oxides on said plurality of conductive contact portions of said at least one substrate, said temperature control device modifies the temperature of said at least one substrate, and said gas source provides hydrogen over said oxides.

52. The system according to claim 51 further comprising a computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device

wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:

(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;

(b) testing functionality of said integrated circuits of said at least one substrate;

(c) burning-in said at least one substrate;

(d) repairing said integrated circuits of said at least one substrate;

(e) programming said integrated circuits of said at least one substrate;

(f) marking a symbol on said at least one substrate; and

,

(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.

53. The system according to claim 49 wherein at least one said first and second modules further comprises:

a gas source for supplying at least a non-oxidizing gas into said at least one module.

54. The system according to claim 49 comprising a handler for moving said first and second substrates.

55. The system according to claim 49 wherein at least one of said modules comprises an electronic circuit board coupled to a computer.

56. The system according to claim 49 wherein said integrated circuits of said at least one substrate are functionally tested, burned-in and configured in said chamber.

57. The system according to claim 49 wherein said at least one module is gas tight.

58. The system according to claim 57 further including said computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device

wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:

(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;

(b) concurrently testing functionality of substantially all of said integrated circuits of said at least one substrate;

(c) concurrently burning-in substantially all of said integrated circuits of said at least one substrate;

(d) concurrently repairing substantially all of said integrated circuits of said at least one substrate,

(e) concurrently programming substantially all of said integrated circuits of said at least one substrate;

(f) marking a symbol on said at least one substrate; and

,

(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.

59. The system according to claim 49 wherein said at least one substrate is a whole semiconductor wafer.

60. The system according to claim 49 further including a second temperature control device for modifying the temperature of said second substrate, wherein said first module and said second module perform same functions simultaneously.

61. The system of claim 46, further comprising said first probing device, including a plurality of probe points for simultaneously contacting substantially all of the contact pads on an integrated circuit wafer;

wherein said integrated test electronics allow each circuit to be individually electrically tested.

62. The system according to claim 61 further comprising:

a gas source for supplying at least a first gas into said system; and

a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.

63. The system according to claim 62 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.

64. The system according to claim 62 wherein said system is a gas tight system.

65. The system according to claim 61 including a plurality of internal modules wherein:

a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer; and

a second one of said internal modules includes

a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,

means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested, and,

a second holding fixture for holding the second wafer.

66. The system according to claim 65 further including a handler for moving said first and second wafers and for moving said first and second probing devices;

wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;

wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and

wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.

67. The system according to claim 61 wherein said integral test electronics comprises integrated circuitry.

68. The system according to claim 67 wherein said integrated circuitry comprises active switching circuits.

69. The system according to claim 61 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.

70. The system according to claim 61 wherein the probing device comprises a membrane including said plurality of probe points.

71. The system according to claim 70 wherein said first control electronics comprises integrated circuitry in the first probing device.

72. The system according to claim 71 wherein said integrated circuitry comprises active switching circuits.

73. The system according to claim 70 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.

74. The system according to claim 70 further comprising.

a gas source for supplying at least a first gas into said system;

a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.

75. The system according to claim 74 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.

76. The system according to claim 74 wherein said system is a gas tight system.

77. The system according to claim 70 including a plurality of internal modules wherein

a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer;

and

a second one of said internal modules includes

a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,

means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested and,

a second holding fixture for holding the second wafer.

78. The system according to claim 77 further including a handler for moving said first and second wafers and for moving said first and second probing devices;

wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;

wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and

wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.

79. The system according to claim 78 wherein said probe points of said first probing device are in contact with said conductive contact portions of said integrated circuits of said first substrate for functional circuit testing, electrical burn-in, repair, or programming wherein

for said functional circuit testing, said computer sends first electrical signals to said first electronic circuit board, said first electronic circuit board sends second electrical signals to said circuits of said first probing device so that third electrical signals are applied to said conductive contact portions of said integrated circuits of said first substrate through said probe points of said first probing device, and fourth electrical signals produced in response to said third electrical signals are transmitted to said computer;

for said electrical burn-in, each of said integrated circuits of said first substrate is tested for a predetermined time period over a range of predetermined temperature and electrical conditions to produce burn-in data;

for said repair, said computer sends electrical signals causing an electrical stimulus to be applied via selected ones of said probe points to cause one of a fuse circuit device and an anti-fuse circuit device to change state; and

for said programming, said computer sends electrical signals causing electrical stimuli to be applied via selected ones of said probe points to cause binary values to be stored non-volatiley in said circuits.

80. The system according to claim 79 wherein

said computer analyzes data corresponding to said fourth electrical signals or said burn-in data and produces circuit repair or circuit programming signals wherein said first probing device performs circuit repair using said circuit repair signals or programs said integrated circuits of said first substrate through said probe points of said first probing device.

81. The system according to claim 80 wherein said computer generates a database from performance data corresponding to each of said integrated circuits of said first substrate for manufacturing control immediately after completion of substrate fabrication.

82. The apparatus of claim 46 further comprising said first probing device.

83. The apparatus of claim 82 wherein said integrated test electronics are passive only.

84. The apparatus of claim 46, wherein said integrated test electronics include active switching circuitry.

85. The apparatus of claim 84, wherein said active switching circuitry causes a given signal line to be coupled to a first probe point at a first time and a second different probe point at a second different time.

86. The apparatus of claim 85, wherein said first and second probe points each correspond to an output pad of an integrated circuit.