Active fail-safe detect circuit for differential receiver

• US 6,288,577 B1
• Filed: 03/02/2001
• Issued: 09/11/2001
• Est. Priority Date: 03/02/2001
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Wong, Anthony Yap
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/681,237
• Time in Patent Office: 193 Days
• Field of Search: 327/52, 327/63, 327/64, 327/65, 327/68, 327/70, 327/76-80, 327/82, 327/89, 327/90, 326/14
• US Class Current: 327/65
• CPC Class Codes: H03K 19/007 Fail-safe circuits
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/10 Compensating for variations in line balance

Abstract

A fail-safe circuit for a differential receiver can tolerate high common-mode voltages. An output from a differential amplifier that receives a V+ and a V− differential signal can be blocked by a NOR gate when the fail-safe condition is detected, such as when the V+, V− lines are open. Pullup resistors pull V+, V− to Vcc when an open failure occurs. A pair of comparators receive a reference voltage on the non-inverting input. Once comparator outputs a high when the V+ line is above the reference voltage, and the other comparator outputs a high when the V− line is above the reference voltage. When both V+ and V− are above the reference voltage, the NOR gate blocks the output from the differential amplifier, providing a fail-safe. Since the reference voltage is very close to Vcc, a high common-mode bias can exist on V+, V− without falsely activating the fail-safe circuit.

Claims

1. A fail-safe differential receiver comprising:

a pair of differential inputs that comprise a first differential input and a second differential input;

a differential amplifier, receiving the first and second differential inputs, for generating a difference output;

a first pullup resistor, coupled between a power supply and the first differential input;

a second pullup resistor, coupled between the power supply and the second differential input;

a first comparator, receiving the first differential input and a reference voltage, for generating a first compare signal;

a second comparator, receiving the second differential input and a reference voltage, for generating a second compare signal;

a combining gate, receiving the first and second compare signals, for generating a blocking signal;

a first reference-generating resistor, coupled between the power-supply and a reference node for the reference voltage;

a second reference-generating resistor, coupled between the reference node and a ground;

wherein a resistance value of the first reference-generating resistor is at least 90% less than a resistance value of the second reference-generating resistor; and

a blocking gate, receiving the difference output from the differential amplifier and the blocking signal, for driving a safe output to a fixed state when the first and second comparators activate the first and second compare signals, but for passing the difference output to the safe output when either the first compare signal of the second compare signal is not activated,

whereby differential inputs are compared to the reference voltage to determine when to block the difference output from the differential amplifier.

2. The fail-safe differential receiver of claim 1 wherein the reference voltage is at

least 90% of a power-supply voltage for the power supply, whereby a high common-mode bias to first and second differential inputs is tolerated without activating the blocking signal.

3. The fail-safe differential receiver of claim 2 wherein the reference voltage is at least 95% of the power-supply voltage.

4. The fail-safe differential receiver of claim 2 wherein the blocking gate and the combining gate are NOR gates.

5. The fail-safe differential receiver of claim 4 wherein the first comparator further comprises a non-inverting input that receives the reference voltage, and an inverting input that receives the first differential input, the first compare signal being activated when the first differential input has a voltage above the reference voltage;

wherein the second comparator further comprises a non-inverting input that receives the reference voltage, and an inverting input that receives the second differential input, the second compare signal being activated when the second differential input has a voltage above the reference voltage.

6. The fail-safe differential receiver of claim 1 further comprising:

a terminating resistor, coupled between the first and second differential inputs, for generating a voltage difference that is detected by the differential amplifier.

7. The fail-safe differential receiver of claim 6 wherein the terminating resistor has a resistance value of 50 to 150 ohms.

8. The fail-safe differential receiver of claim 7 wherein the first and second pullup resistors have resistance values that are at least a hundred times greater than the resistance value of the terminating resistor.

9. A differential receiver comprising:

a first differential input;

a second differential input;

differential amplifier means, responsive to the first and second differential inputs, for generating a difference signal in response to a voltage difference between the first and second differential inputs;

first compare means, coupled to the first differential input, for determining when the first differential input is outside of a voltage limit;

second compare means, coupled to the second differential input, for determining when the second differential input is outside of the voltage limit;

first reference-generating resistor means for generating a reference voltage, coupled between the power-supply and a reference node for the reference voltage;

second reference-generating resistor means for generating the reference voltage, coupled between the reference node and a ground;

wherein a resistance value of the first reference-generating resistor means is at least 90% less than a resistance value of the second reference-generating resistor means; and

combining means, coupled to the first and second compare means, for blocking the difference signal from the differential amplifier means when both the first differential input and the second differential input are outside of the voltage limit;

whereby the difference signal from the differential amplifier means is blocked when both the first differential input and the second differential input are outside of the voltage limit.

10. The differential receiver of claim 9 further comprising:

first resistor means, coupled to the first differential input, for driving the first differential input to a fixed voltage when the first differential input is not driven by a transmitter;

second resistor means, coupled to the second differential input, for driving the second differential input to a fixed voltage when the second differential input is not driven by a transmitter.

11. The differential receiver of claim 10 wherein the first reference-generating resistor means and the second reference-generating resistor means comprise a voltage limit means for generating the reference voltage, the reference voltage indicating the voltage limit.

12. The differential receiver of claim 10 further comprising:

load resistor means, coupled between the first and second differential inputs, for generating a voltage between the first and second differential inputs.

13. The differential receiver of claim 10 wherein the differential receiver is a low-voltage differential signaling (LVDS) receiver.

14. The differential receiver of claim 10 wherein the fixed voltage is outside the voltage limit compared by the first and second comparators.

15. The differential receiver of claim 14 wherein the first resistor means and the second resistor means are coupled to a power supply;

wherein the voltage limit is an upper limit.

16. A differential receiver with open-cable detection comprising:

a cable input having a first differential line and a second differential line;

a load resistor coupled between the first and second differential lines to generate a voltage difference;

a differential amplifier for amplifying the voltage difference across the load resistor, the differential amplifier receiving the first and second differential lines and generating a difference output;

p1 a first resistor coupled to the first differential line, for driving the first differential line to a fixed voltage when the first differential line is open;

a second resistor coupled to the second differential line, for driving the second differential line to a fixed voltage when the second differential line is open;

a first comparator, receiving the first differential line and coupled to a reference node, for comparing a voltage on the first differential line to a reference voltage on the reference node and generating a first compare output;

a second comparator, receiving the second differential line and coupled to the reference node, for comparing a voltage on the second differential line to the reference voltage on the reference node and generating a second compare output;

a first reference-generating resistor, coupled between the power-supply and the reference node for the reference voltage;

a second reference-generating resistor, coupled between the reference node and a ground;

wherein a resistance value of the first reference-generating resistor is at least 90% less than a resistance value of the second reference-generating resistor; and

blocking logic, receiving the first and second compare outputs and the difference output, for blocking the difference output and driving a final output with a constant signal when both the first and second differential lines are beyond a voltage limit determined by the reference voltage, but otherwise passing the difference output to the final output.

17. The differential receiver with open-cable detection of claim 16 wherein the blocking logic comprises:

a first gate, receiving the first and second compare outputs, for generating a blocking signal;

a second gate, receiving the blocking signal and the difference output, for generating the final output.

18. The differential receiver with open-cable detection of claim 17 wherein the second gate comprises a NOR gate and an inverter.

19. The differential receiver with open-cable detection of claim 18 wherein the fixed voltage is a power-supply voltage, and wherein the voltage reference is within 10% of the power-supply voltage.