CMOS on-chip precision voltage reference scheme

• US 6,288,602 B1
• Filed: 12/29/1995
• Issued: 09/11/2001
• Est. Priority Date: 06/25/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hoffman, Charles R.
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US08/580,778
• Time in Patent Office: 2,083 Days
• Field of Search: 307/262, 307/269, 307/296.1, 307/296.2, 307/296.4, 307/296.5, 307/296.6, 307/296.7, 307/296.8, 307/490, 307/491, 307/494, 328/63, 328/155, 323/313, 365/189.03, 365/189.07
• US Class Current: 327/541
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A process friendly precision voltage generator for use in a digital/analog system or the like, includes a modified phase lock loop (MPLL) and a frequency control system for adjusting the frequency of the MPLL until a desired reference voltage is obtained at an output node of the loop filter. The frequency of the phase lock loop is then locked to the frequency, at which the desired reference voltage has been obtained.

Claims

1. A computer system comprising:

a bus means for providing bidirectional communications; and

at least two modules coupled to the bus means with each one of said two modules having an interface unit for connecting to the bus means, a logic means for generating at least one desired function coupled to the interface unit and a reference voltage generator for generating and applying a predetermined reference voltage to the interface unit, said reference voltage generator including a phase lock loop, a frequency adjustment means coupled to the phase lock loop, for adjusting frequencies of the phase lock loop until a frequency is set whereat the reference voltage is established and a circuit arrangement for locking the frequency to one of the frequencies which produce the reference voltage.

2. The computer system of claim 1 wherein the interface unit includes a driver circuit with an input terminal coupled to the logic means and an output terminal;

a pull-down FET device having a gate electrode connected to the driver circuit and a collector electrode connected to the bus; and

a receiver having an output coupled to the logic means, a first input coupled to the FET device and a second input coupled to the reference voltage generator.

3. The computer system of claim 1 wherein the phase lock loop includes a phase detector circuitry having an output node and a pair of input nodes;

a charge pump circuitry with an input coupled to the output node and a charge pump output node;

a loop filter circuitry with an output loop filter node for providing the reference voltage and an input loop filter node connected to the charge pump output node; and

a VCO with an input node coupled to the output loop filter to node and a VCO output node.

4. The computer system of claim 3 wherein the frequency adjustment means includes a means for generating a clock signal;

said means having a clock output;

a first divide means with a first divide input connected to the clock output and a first divide output connected to one input of the phase detector circuitry;

a second divide means with a second divide input node coupled to the VCO output node; and

a second divide output node connected to another input of the phase detector circuitry; and

a digital control logic with separate outputs connected to the first divide means and the second divide means.

5. A reference voltage generator comprising:

a phase lock loop;

a frequency adjustment means coupled to the phase lock loop;

said frequency adjustment means operable for adjusting loop frequency until a desired reference voltage is generated at a selected node of said phase lock loop; and

a circuit arrangement, operatively coupled to the frequency adjustment means, for locking the loop frequency at a value whereat the desired reference voltage has been attained.

6. The reference voltage generator of claim 5 wherein the phase lock loop includes a phase detector with a pair of input nodes and an output node;

a charge pump coupled to the output node;

a loop filter circuitry having a reference node for supplying the reference voltage and a loop filter input node coupled to the charge pump;

a VCO having a VCO input node coupled to the reference node and a VCO output node; and

a divide by N circuitry, N being an integer, coupled to the VCO output node and an input of the phase detector.

7. The reference voltage generator of claim 6 wherein the frequency adjustment means includes an oscillator means for generating clock signals;

a divide by M circuitry, M being an integer, for interconnecting the clock signals to another input of said phase detector; and

a digital control logic means for supplying signals to the divide by M circuitry and divide by N circuitry, respectively.

9. The reference voltage generator of claim 5 wherein the frequency adjustment means includes an oscillator for generating clock signals;

a divide by M circuitry, M being an integer, for interconnecting the clock signals to an input of phase detector in said phase lock loop; and

a logic control circuit for supplying signals to the divide by M circuitry.

10. The reference voltage generator of claim 9 wherein the logic control circuit includes a ripple counter with a plurality of output ports connected to the divide by M circuitry;

and an input port for receiving input clock pulses for toggling selected ones of the plurality of output ports.

11. The reference voltage generator of claim 10 wherein the circuit arrangement includes a plurality of resistors connected in parallel with each resistor having a first end to be connected to a first voltage source and a second end connected to one end of a laser fuse and another end of said laser fuse to be connected to a second voltage source wherein each one of said serially connected resistor and fuse is connected to selected ones of the plurality of output ports and selected ones of said laser fuse are opened when a count in the ripple counter is at the value where the desired reference voltage is attained.

8. A VLSI module comprising:

a circuit means for generating at least one desired function;

a reference voltage generating means coupled to the circuit means, said reference voltage generating means having a phase lock loop therein, a frequency adjustment means for adjusting loop frequency until a desired reference voltage is provided at a selected node of the phase lock loop and a circuit arrangement, operatively coupled to the frequency adjustment means, for locking the loop frequency to a value at which a desired voltage is attained; and

an interface means for coupling the circuit means to a bus.

12. A method for generating a fixed reference voltage comprising the steps of:

(a) providing a phase lock loop with a feed forward path including a phase detector with an output connected to an input of a charge pump, an output of the charge pump connected to an input of a loop filter and an output of the loop filter providing the fixed reference voltage and connected to a feed back path;

(b) providing a divide by M circuit arrangement having a first input for receiving clock signals, an output connected to the phase detector and data inputs for receiving data;

(c) providing a first circuit arrangement for generating the data;

(d) providing a second circuit arrangement for locking the data to a fixed value;

(e) operatively connecting the first circuit arrangement and second circuit arrangement to the data inputs;

(f) applying the clock signals to the first input;

(g) applying clock signals to the first circuit arrangement until the fixed reference voltage is generated; and

(h) using a count resulting from the data generated in step (c) to activate the second circuit arrangement to permanently lock the phase lock loop to a frequency of which the fixed reference voltage is attained.