Bias circuits for depletion mode field effect transistors

• US 6,288,613 B1
• Filed: 06/15/2000
• Issued: 09/11/2001
• Est. Priority Date: 06/15/2000
• Status: Expired due to Term

• Current Assignee: Ciena Corporation
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Bennett, Jeffrey H.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/594,583
• Time in Patent Office: 453 Days
• Field of Search: 330/277, 330/288, 330/290
• US Class Current: 330/296
• CPC Class Codes: H03F 1/306 in junction-FET amplifiers H03F1/303, H03F1/305, H03F1/309 take precedence

Abstract

A bias circuit for providing a gate voltage for a first depletion mode FET operating on RF signals comprises a second similar FET in a source-follower configuration with zero gate-source voltage to conduct a drain-source current Idss via a source resistor. A third depletion mode FET has its gate connected to receive a voltage dropped across this source resistor, its source coupled to a diode whose forward voltage drop constitutes a reference voltage, and its drain connected to a second resistor, a voltage drop across which due to the drain-source current of the third FET constitutes a gate-source voltage for the first FET. The bias circuit compensates for process variations in manufacture of the first FET, and also provides temperature compensation.

Claims

1. A bias circuit for providing a gate voltage for a first depletion mode FET (field effect transistor) to be controlled, the bias circuit comprising:

a second depletion mode FET having similar characteristics to the first FET, the second FET having its gate coupled to its source for conducting a drain-source current via a resistor to produce a first voltage dependent on the drain-source current; and

a comparator for comparing the first voltage with a reference voltage to produce said gate voltage in dependence upon differences between the first voltage and the reference voltage, so that an increase in said drain-source current of the second FET results in a change of said gate voltage of the first FET to reduce drain-source current of the first FET thereby to compensate for process variations of said first and second FETs.

2. A bias circuit as claimed in claim 1 and including a forward biassed diode, wherein the reference voltage comprises a forward voltage drop of the diode.

3. A bias circuit as claimed in claim 2 wherein the diode is constituted by a diode-connected FET.

4. A bias circuit as claimed in claim 1 wherein the second FET has a source-follower configuration with said resistor connected to its source.

5. A bias circuit as claimed in claim 4 wherein the second FET has its gate coupled to its source via a source degeneration resistor.

6. A bias circuit as claimed in claim 1 wherein the comparator comprises a third depletion mode FET having similar characteristics to the first and second FETs, its gate coupled to the resistor to receive the first voltage, its source arranged to receive the reference voltage, and its drain connected to a further resistor for conducting drain-source current of the third FET via the further resistor to produce said gate voltage for the first FET at the drain of the third FET.

7. A bias circuit as claimed in claim 6 and including a diode connected to the source of the third FET and forward biassed by the drain-source current of the third FET, the reference voltage comprising a forward voltage drop of the diode.

8. A bias circuit as claimed in claim 7 wherein the diode is constituted by a diode-connected FET.

9. A bias circuit as claimed in claim 6 wherein the second FET has a source-follower configuration with said resistor connected to its source.

10. A bias circuit as claimed in claim 6 and including a second comparator for comparing the first voltage with the reference voltage to produce a second gate voltage, for another depletion mode FET to be controlled and having similar characteristics to the first FET, in dependence upon differences between the first voltage and the reference voltage, wherein the second comparator comprises a fourth depletion mode FET having similar characteristics to the first and second FETs, its gate coupled to the resistor to receive the first voltage, its source arranged to receive the reference voltage, and its drain connected to another resistor for conducting drain-source current of the fourth FET via said another resistor to produce said second gate voltage at the drain of the fourth FET.

11. A bias circuit as claimed in claim 10 wherein at least one of the third and fourth FETs has its source connected to a source degeneration resistor via which it receives said reference voltage.

12. A bias circuit as claimed in claim 1 and including a second comparator for comparing the first voltage with the reference voltage to produce a second gate voltage, for another depletion mode FET to be controlled and having similar characteristics to the first FET, in dependence upon differences between the first voltage and the reference voltage.

13. A bias circuit for providing a gate voltage for a first depletion mode FET (field effect transistor) to be controlled, the bias circuit comprising:

a second depletion mode FET having similar characteristics to the first FET, the second FET having a source-follower configuration with its gate coupled to its source for conducting a drain-source current via a first resistor to produce a first voltage dependent on the drain-source current across the first resistor;

a third depletion mode FET having its gate coupled to the first resistor to receive the first voltage, its source arranged to receive a reference voltage, and its drain connected to a second resistor for conducting drain-source current of the third FET via said second resistor to produce said gate voltage for the first FET at the drain of the third FET.

14. A bias circuit as claimed in claim 13 wherein the second FET has its gate coupled to its source via a source degeneration resistor.

15. A bias circuit as claimed in claim 13 and including a diode connected to the source of the third FET and forward biassed by the drain-source current of the third FET, the reference voltage comprising a forward voltage drop of the diode.

16. A bias circuit as claimed in claim 15 wherein the diode is constituted by a diode-connected FET.

17. A bias circuit as claimed in claim 15 and including a fourth depletion mode FET having its gate coupled to the first resistor to receive the first voltage, its source coupled to the diode to receive the reference voltage, and its drain connected to a third resistor for conducting drain-source current of the fourth FET via said third resistor to produce another gate voltage, for another FET to be controlled and having similar characteristics to the first and second FETs, at the drain of the fourth FET.

18. A bias circuit as claimed in claim 17 wherein at least one of the third and fourth FETs has its source connected to the diode via a source degeneration resistor.

19. A method of compensating for process variations to which a first depletion mode FET is subject by controlling a gate voltage of the first FET, comprising the steps of:

biassing a second depletion mode FET, subject to substantially the same process variations as the first FET, with an approximately zero gate-source voltage so that it conducts a drain-source current via a first resistor to produce a first voltage;

supplying the first voltage and a reference voltage to the gate and source respectively of a third depletion mode FET whereby the third FET conducts a drain-source current via a second resistor coupled to the drain of the third FET; and

deriving the gate voltage of the first FET from a junction between the drain of the third FET and the second resistor.

20. A method as claimed in claim 19 and further comprising the step of producing the reference voltage from a forward voltage drop of a diode which is coupled to the source of the third FET and conducts drain-source current of the third FET.