Method and circuit for driving display device

• US 6,288,697 B1
• Filed: 11/13/1997
• Issued: 09/11/2001
• Est. Priority Date: 11/15/1996
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Eto, Sunao, Okada, Hisao
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Frenel, Vanel
• Application Number:
  US08/969,447
• Time in Patent Office: 1,398 Days
• Field of Search: 345/87, 345/98, 345/100, 345/95, 345/97, 345/99, 345/212, 345/213, 345/94
• US Class Current: 345/87
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

According to the present invention, a method for driving a display device, including a display panel having a plurality of pixels and a plurality of data lines connected to the respective pixels, is provided. The method includes the steps of: sampling data in a first horizontal interval; storing the data sampled in the first horizontal interval; updating output data based on the stored data in the middle of sampling next data in a second horizontal interval next to the first horizontal interval; and outputting a voltage corresponding to the output data to a corresponding one of the data lines.

Claims

1. A method for driving a display device including a display panel having a plurality of pixels and a plurality of data lines connected to the respective pixels, comprising the steps of:

sampling data in a first horizontal interval;

storing the data sampled in the first horizontal interval;

updating output data based on the stored data during sampling of a next data in a second horizontal interval immediately following the first horizontal interval, wherein the updated output data is based only on data sampled in the first horizontal interval; and

outputting a voltage corresponding to the updated output data to a corresponding one of the data lines from a second half following a first half of the second horizontal interval to a first half of a third horizontal interval following the second horizontal interval, wherein inverse polarities are output to a corresponding one of the data lines in the second horizontal interval and in the third horizontal interval.

8. The method as defined in claim 1, wherein said output data is updated at substantially a midpoint of said second horizontal interval.

2. A circuit for driving a display device including a display panel having a plurality of pixels and a plurality of data lines connected to the respective pixels, comprising:

a sampling memory for storing data sampled in a first horizontal interval;

a transfer memory for storing data output from the sampling memory in response to a transfer pulse;

a holding memory for storing data output from the transfer memory in response to an output pulse, wherein the holding memory only holds data sampled from the first horizontal interval; and

an output circuit section for outputting a voltage corresponding to the data stored in the holding memory to a corresponding one of the data lines,

wherein the output pulse is supplied to the holding memory during sampling of a next data in a second horizontal interval immediately following the first horizontal interval, outputting a voltage corresponding to the updated output data to a corresponding one of the data lines from a second half following a first half of the second horizontal interval to a first half of a third horizontal interval following the second horizontal interval, wherein inverse polarities are output to a corresponding one of the data lines in the second horizontal interval and in the third horizontal interval.

3. A circuit according to claim 2, wherein the transfer pulse is supplied to the transfer memory after the sampling of the data has been completed in the first horizontal interval and before the sampling of the next data is started in the second horizontal interval.

4. A circuit according to claim 2, wherein the data stored in the transfer memory includes a first bit portion and a second bit portion,

and wherein the holding memory stores the first bit portion of the data,

and wherein the output circuit section outputs a voltage corresponding to the first bit portion of the data stored in the holding memory and also corresponding to the second bit portion of the data stored in the transfer memory to the data line.

9. The circuit according to claim 2, wherein the output pulse is supplied to the holding memory at substantially a midpoint of said second horizontal interval.

5. A circuit for driving a display device including a display panel having a plurality of pixels and a plurality of data lines connected to the respective pixels, comprising:

a sampling memory for storing data sampled in a first horizontal interval;

a holding memory section including a first holding memory and a second holding memory, for storing data output from the sampling memory into one of the first holding memory and the second holding memory, in response to a transfer pulse;

a selection circuit section for selectively outputting one of the data stored in the first holding memory and the data stored in the second holding memory, in accordance with a level of an output pulse, wherein data selected by the selection circuit section is based only on data sampled in the first horizontal interval; and

an output circuit section for outputting a voltage corresponding to the data selected by the selection circuit section to a corresponding one of the data lines,

wherein the level of the output pulse changes during sampling of a next data in a second horizontal interval immediately following the first horizontal interval, outputting a voltage corresponding to the updated output data to a corresponding one of the data lines from a second half following a first half of the second horizontal interval to a first half of a third horizontal interval following the second horizontal interval, wherein inverse polarities are output to a corresponding one of the data lines in the second horizontal interval and in the third horizontal interval.

6. A circuit according to claim 5, wherein the level of the transfer pulse changes after the sampling of the data has been completed in the first horizontal interval and before the sampling of the next data is started in the second horizontal interval.

7. A circuit according to claim 5, wherein the data stored in the sampling memory includes a first bit portion and a second bit portion,

and wherein the first holding memory stores the first bit portion and the second bit portion of the data,

and wherein the second holding memory stores the first bit portion of the data,

and wherein the selection circuit section selectively outputs one of the first bit portion stored in the first holding memory and the first bit portion stored in the second holding memory,

and wherein the output circuit section outputs a voltage corresponding to the first bit portion of the data selected by the selection circuit section and also corresponding to the second bit portion of the data stored in the first holding memory to the data line.

10. The circuit according to claim 5, wherein the level of the output pulse changes at substantially a midpoint of said second horizontal interval.