System and method for reducing peak current and bandwidth requirements in a display driver circuit

• US 6,288,712 B1
• Filed: 11/14/1997
• Issued: 09/11/2001
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Aurora SFC Systems (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Hudson, Edwin Lyle, Pinkham, Raymond, Worley, W. Spencer III, Campbell, John Gray
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Nguyen, Jimmy H.
• Application Number:
  US08/970,665
• Time in Patent Office: 1,397 Days
• Field of Search: 345/214, 345/215, 345/204, 345/33, 345/42, 345/51, 345/90, 345/93, 345/98, 345/100, 345/103, 345/92, 345/87, 345/88, 345/99
• US Class Current: 345/204
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A display driver circuit for reducing system interface band width requirements and peak current requirements includes a select line sequencer, for providing a series of select line addresses on an address terminal set, and a select line decoder coupled to the address terminal set, for decoding each of the select line addresses and asserting an update signal on a corresponding one of a plurality of output terminals. Optionally, the select line sequencer generates a series of select sub-line addresses, and the select line decoder is a select sub-line decoder. An optional select address register receives initial select addresses from a system and provides the initial select addresses to the select line sequencer. An alternate display driver circuit including a select line sequencer and a select sub-line sequencer is also described.

Claims

1. A display driver circuit for driving a display including an array of pixel cells, said display driver circuit comprising:

a plurality of write signal output terminals for providing write signals to said display to latch data into said display;

a select sequencer for providing at an output a series of select addresses;

a select address register for receiving an initial select address from a system and coupled to said select sequencer for providing said initial select address to said select sequencer; and

a select decoder having an input, coupled to said output of said select sequencer, and a plurality of select signal output terminals, for decoding each said select address and asserting a pixel update signal on a corresponding one of said select signal output terminals, said pixel update signal on said one of said select signal output terminals causing the pixel cells of an associated row to assert the previously latched data onto their associated pixel electrodes.

2. A display driver circuit according to claim 1, wherein said select address register includes an input terminal for receiving another initial select address.

3. A display driver circuit according to claim 2, wherein:

said select sequencer includes a control input terminal;

said select sequencer outputs a next address of said series of select

addresses responsive to receipt of a first control signal; and

said select sequencer outputs a new series of select addresses starting from said another initial select address responsive to receipt of a second control signal.

4. A display driver circuit according to claim 2, wherein said another initial select address is different than said initial select address.

5. A display driver circuit according to claim 1, wherein:

said select sequencer includes a select sub-line sequencer for providing at an output a series of select sub-line addresses; and

said select decoder includes a select sub-line decoder having an input, coupled to said output of said select sub-line sequencer, and a plurality of output terminals each coupled to a respective one of a set of said output terminals of said select decoder, for decoding each said select sub-line address and asserting an update signal on a corresponding one of said set of output terminals.

6. A display driver circuit according to claim 1, wherein said series of select addresses comprises a monotonic, increasing series.

7. A display driver circuit according to claim 1, wherein:

said select sequencer includes a select line sequencer for providing at an output a series of select line addresses; and

said select decoder includes a select line decoder having an input, coupled to said output of said select line sequencer, and a plurality of output terminals each coupled to a respective one of a set of said output terminals of said select decoder, for decoding each said select line address and asserting an update signal on a corresponding one of said set of output terminals.

8. A display driver circuit according to claim 7, wherein:

said select sequencer further includes a select sub-line sequencer for providing at an output a series of select sub-line addresses; and

said select decoder includes a select sub-line decoder having an input, coupled to said output of said select sub-line sequencer, and a plurality of output terminals each coupled to a respective one of a second set of said output terminals of said select decoder, for decoding each said select sub-line address and asserting an update signal on a corresponding one of said second set of output terminals.

9. In a display driver circuit for driving a display including an array of pixel cells, said display diver circuit having a plurality of write signal output terminals and a plurality of select signal output terminals, said display driver circuit coupled to a system which provides update commands and display addresses of blocks which are to be updated, a method for updating a display comprising the steps of:

asserting a series of write signals on said plurality of write signal output terminals to latch data into said display;

receiving a first initial select address from said system;

generating a series of select addresses based on said first initial select address;

decoding each of said select addresses of said series of select addresses; and

asserting a series of pixel update signals on a first group of said plurality of select signal output terminals, each select signal output terminal of said first group corresponding to an associated select address, said pixel update signals on said first group of select signal output terminals causing the pixel cells of an associated row to assert the previously latched data onto their associated pixel electrodes.

10. A method according to claim 9, wherein said method for driving said display further comprises the steps of:

receiving another initial select address; and

generating another series of select addresses based on said another initial select address.

11. A method according to claim 10, wherein said method for driving said display further comprises the steps of:

outputting said another initial select address;

generating a second select address based on said another initial select address; and

outputting said second select address.

12. A method according to claim 10, wherein said step of receiving another initial select address includes the steps of:

receiving a block address from said system; and

generating said another initial select address based on said block address.

13. A method according to claim 10, wherein said another initial select address is different than said first initial select address.

14. A method according to claim 9, wherein said step of generating a series of select addresses comprises the steps of:

outputting said initial select address responsive to a first update command;

generating a second select address based on said initial select address; and

outputting said second select address.

15. A method according to claim 9, wherein said step of receiving said initial select address includes the steps of:

receiving a block address from said system; and

generating said initial select address based on said block address.

16. A method according to claim 9, wherein said select addresses comprise select line addresses.

17. A method according to claim 16, further comprising the steps of:

generating a series of select sub-line addresses;

decoding each of said select sub-line addresses of said series of select sub-line addresses; and

asserting an update signal on a second group of said plurality of output terminals, each output terminal of said second group corresponding to an associated select sub-line address.

18. A method according to claim 9, wherein said select addresses comprise select sub-line addresses.