Optimizing the performance of asynchronous bus bridges with dynamic transactions

• US 6,289,406 B1
• Filed: 11/06/1998
• Issued: 09/11/2001
• Est. Priority Date: 11/06/1998
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Chambers, Peter, Adusumilli, Swaroop, Meiyappan, Subramanian S.
• Primary Examiner(s): Myers, Paul R.
• Application Number:
  US09/187,325
• Time in Patent Office: 1,040 Days
• Field of Search: 710/110, 710/107, 710/126, 710/118, 710/125, 710/105, 710/129, 737/102
• US Class Current: 710/107
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period. The target device is adapted to maintain the access to the initiator device during the dynamic target latency period. Thus, in accordance with the present invention, the target latency is dynamically measured and used to optimize the retry behavior of the initiator and target devices.

Claims

1. A system for completing a present read transaction between an initiator device and a host memory device in a computer system, said system comprising:

a bus;

a bus bridge device, said bus bridge device comprising;

a target device, said target device coupled to said initiator device via said bus; and

a timer mechanism coupled to said target device; and

said host memory device coupled to said bus bridge device;

said initiator device adapted to assert an access to said target device, such that said present read transaction is initiated;

said timer mechanism adapted to measure target latency for one or more read transactions contiguously preceding said present read transaction, said timer mechanism further adapted to use said target latency to determine a dynamic target latency period and to update said dynamic target latency period after each read transaction; and

said bus bridge device adapted to maintain said access to said initiator device during said dynamic target latency period, thereby facilitating completion of said present read transaction.

2. The system of claim 1 wherein said initiator device, said target device, and said bus are peripheral component interconnect (PCI) devices and said bus bridge device is a PCI-to-host bridge device.

3. The system of claim 1 wherein said target device and said timer mechanism are fabricated as a single device.

4. The system of claim 1 wherein said target device inserts one or more wait states to maintain said access to said initiator device during said dynamic target latency period.

5. The system of claim 1 wherein said timer mechanism makes a count of clock pulses that occur during each of said one or more read transactions.

6. The system of claim 5 wherein said dynamic target latency period is based on said count of clock pulses corresponding to a read transaction most recently preceding said present read transaction.

7. The system of claim 5 wherein said dynamic target latency period is based on an average of said count of clock pulses corresponding to a plurality of read transactions preceding said present read transaction.

8. The system of claim 1 wherein a threshold target latency is established based on said dynamic target latency period, and said access is terminated when target latency for said present read transaction exceeds said threshold target latency and data corresponding to said present read transaction are not received by said bus bridge device.

9. The system of claim 1 further comprising a sideband signal link between said timer mechanism and said initiator device, said sideband signal link used to communicate said dynamic target latency period to said initiator device.

10. The system of claim 9 wherein said initiator device is adapted to delay a retry of said access until said dynamic target latency period is exceeded.

11. A system for completing a present read transaction between an initiator device and a host memory device in a computer system, said system comprising:

a bus;

a bus bridge device, said bus bridge device comprising;

a target device, said target device coupled to said initiator device via said bus; and

a timer mechanism coupled to said target device, wherein said timer mechanism is also coupled to said initiator device; and

said host memory device coupled to said bus bridge device;

said timer mechanism adapted to measure target latency for one or more read transactions contiguously preceding said present read transaction, said timer mechanism further adapted to use said target latency to determine a dynamic target latency period and to update said dynamic target latency period after each read transaction; and

said initiator device adapted to delay a retry of said access until said dynamic target latency period is exceeded.

12. The system of claim 11 wherein said initiator device, said target device, and said bus are peripheral component interconnect (PCI) devices and said bus bridge device is a PCI-to-host bridge device.

13. The system of claim 11 wherein said timer mechanism and said initiator device are coupled via a sideband signal link.

14. The system of claim 11 wherein said timer mechanism makes a count of PCI clock pulses that occur during each of said one or more read transactions.

15. The system of claim 14 wherein said dynamic target latency period is based on said count of PCI clock pulses corresponding to a read transaction most recently preceding said present read transaction.

16. The system of claim 14 wherein said dynamic target latency period is based on an average of said count of clock pulses corresponding to a plurality of read transactions preceding said present read transaction.

17. The system of claim 11 wherein said target device is coupled to said timer mechanism.

18. The system of claim 17 wherein said bus bridge device is adapted to maintain said access to said initiator device during said dynamic target latency period.

19. The system of claim 17 wherein said target device inserts one or more wait states to maintain said access to said initiator device during said dynamic target latency period.

20. The system of claim 17 wherein a threshold target latency is established based on said dynamic target latency period, and said access is terminated when target latency for said present read transaction exceeds said threshold target latency and data corresponding to said present read transaction are not received by said bus bridge device.

21. The system of claim 17 wherein said target device and said timer mechanism are fabricated as a single device.

22. In a peripheral component interconnect (PCI) bus system comprising a PCI initiator device coupled to a host memory device via a bus bridge device, said bus bridge device comprising a timer mechanism coupled to a PCI target device, a method for completing a present read transaction between said PCI initiator device and said host memory device, said method comprising the steps of:

a) said timer mechanism measuring target latencies for one or more read transactions contiguously preceding said present read transaction, said timer mechanism coupled to said PCI target device;

b) said timer mechanism determining a dynamic target latency period using said target latencies;

wherein said dynamic target latency period is updated after each read transaction; and

c) said PCI initiator device asserting an access, such that said present read transaction is initiated;

d) said PCI target device claiming said access;

e) using said dynamic target latency period to specify when said access is to be retried.

23. The method of claim 22 wherein said PCI target device and said timer mechanism are fabricated as a single PCI device.

24. The method of claim 22 wherein step a) further comprises said timer mechanism making a count of clock pulses that occur during each of said one or more read transactions preceding said present read transaction.

25. The method of claim 22 wherein step b) further comprises said timer mechanism using target latency for a read transaction most recently preceding said present read transaction to determine said dynamic target latency period.

26. The method of claim 22 wherein step b) further comprises said timer mechanism averaging target latencies for a plurality of read transactions preceding said present read transaction to determine said dynamic target latency period.

27. The method of claim 22 wherein step e) further comprises the steps of:

said PCI target device maintaining said access during said dynamic target latency period, thereby facilitating completing of said present read transaction; and

said PCI target device retrying said access after said dynamic target latency period is exceeded.

28. The method of claim 22 wherein step e) further comprises the steps of:

said PCI target device retrying said access after claiming said access; and

said PCI initiator device retrying said access after said dynamic target latency period is exceeded, thereby facilitating completion of said present read transaction.