Bus interface with address mask register for transferring selected data from one bus to another

• US 6,289,408 B1
• Filed: 05/08/1995
• Issued: 09/11/2001
• Est. Priority Date: 05/08/1995
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Regal, Michael L.
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US08/437,463
• Time in Patent Office: 2,318 Days
• Field of Search: 395/166, 395/279, 395/281, 395/421.01, 395/288, 395/287, 395/308, 710/100, 710/126
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4217 with synchronous protocol

Abstract

A method and system for selectively permitting address values to pass between two buses. Portions of the address values are used to select data in a mask register. The determination of whether to pass the address value is made on the basis of the mask register value ultimately selected.

Claims

1. An address mask register for defining a range of addresses a bus interface will respond to, said addresses being a subset of an address space divided into a plurality of coarse regions and a plurality of fine regions, said address mask resister comprising:

a coarse address select field for defining which of said plurality of coarse regions of memory include addresses to be transferred from a first bus to a second bus by the bus interface; and

a fine address select field for defining which of said plurality of fine regions have addresses to be transferred from the first bus to the second bus by the bus interface.

2. An address mask register according to claim 1, wherein said coarse address select field contains 16 bits and said fine address select field contains 16 bits.

3. An address mask register according to claim 1, wherein a coarse region defines a 256 MByte region of memory.

4. An address mask register according to claim 1, wherein a fine region defines a 16 MByte region of memory.

5. Apparatus for interfacing a first bus and a second bus, said interface comprising:

a register for storing mask data; and

a first multiplexer arranged to receive a first part of the contents of said register as respective data inputs and arranged to receive a first part of an address value from said first bus as a select input, for outputting a first value from said first part of said register selected on the basis of said first part of said address value;

a second multiplexer arranged to receive a second part of the contents of said register as respective data inputs and arranged to receive a second part of an address value from said first bus as a select input, for outputting a second value from said second part of said register selected on the basis of said second part of said address value;

a comparer for comparing said first part of said address with a predetermined value; and

a third multiplexer arranged to receive said first value and said second value as respective data inputs and arranged to receive results from said comparer as a select input, for outputting one of said first value and said second value selected on the basis of said results from said comparer,

wherein said interface determines whether to pass said address value to said second bus on the basis of the output of said third multiplexer.

6. A method of using a bus interface to control transfer of address values between a first system bus and a second system bus, the method comprising the steps of:

a step performed by a system processor of programming an address mask register in said bus interface with data indicating

a first set of addresses for which said bus interface will pass address values from said first system bus to said second system bus but not from said second system bus to said first system bus and

a second set of addresses different from said first set of addresses for which said bus interface will pass address values from said second system bus to said first system bus but not from said first system bus to said second system bus;

a step performed by said bus interface of receiving a transfer request with an associated address from one of said first system bus and said second system bus to transfer data from one bus to the other;

a step performed by said bus interface of comparing said address associated with said request with said data programmed into said address mask register to determine if said address is in said first set of addresses or said second set of addresses; and

a step performed by said bus interface of

transferring said address from said first system bus to said second system bus only if the request was received from said first system bus to transfer to said second system bus and said comparing step determines that said address is in said first set of addresses,

or, alternatively,

transferring said address from said second system bus to said first system bus only if the request was received from said second system bus to transfer to said first system bus and said comparing step determines that said address is in said second set of addresses.

7. A computer system comprising:

a first system bus;

a second system bus; and

a bus interface connected between said first system bus and said second system bus for controlling transfer of address values between said first system bus and said second system bus, said bus interface including

an address mask register programmed with data indicating a first set of addresses for which said bus interface will pass address values from said first system bus to said second system bus but not from said second system bus to said first system bus and a second set of addresses different from said first set of addresses for which said bus interface will pass address values from said second system bus to said first system bus but not from said first system bus to said second system bus and

a comparer which compares an address associated with a transfer request with said data programmed into said address mask register to determine if said address is in said first set of addresses or said second set of addresses,

wherein said bus interface transfers said address from said first system bus to said second system bus only if the request was received from said first system bus to transfer to said second system bus and said comparer determines that said address is in said first set of addresses, or, alternatively, transfers said address from said second system bus to said first system bus only if the request was received from said second system bus to transfer to said first system bus and said comparer determines that said address is in said second set of addresses.

8. A computer system as claimed in claim 7 wherein said address mask register includes a coarse address select field which defines which of a plurality of coarse regions of memory include addresses in said first set and a fine address select field which defines which of a plurality of fine regions of memory have addresses in said first set.

9. A computer system according to claim 8, wherein said coarse address select field contains 16 bits and said fine address select field contains 16 bits.

10. An address mask register according to claim 8, wherein a coarse region defines a 256 MByte region of memory.

11. An address mask register according to claim 8, wherein a fine region defines a 16 MByte region of memory.