Intelligent memory devices for transferring data between electronic devices

• US 6,289,421 B1
• Filed: 05/21/1999
• Issued: 09/11/2001
• Est. Priority Date: 05/21/1999
• Status: Expired due to Fees

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Szep, Steven C., Ali, Syed S., Hobbi, Mohd Majed
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US09/316,215
• Time in Patent Office: 844 Days
• Field of Search: 710/57, 711/149, 711/131, 711/168, 345/518
• US Class Current: 711/149
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

Intelligent memory devices allow for the transfer of data between two or more electronic devices, such as digital signal processors and microcontrollers. The memory devices may be designed as dual port memory devices capable of sending/receiving synchronous, serial data. The use of serial data reduces the pin count of the memory devices and those connected to it. The memory devices also utilize a dedicated pair of data bits and memory pointers to carry out management of the memory and data transfers allowing connected devices to reduce the amount of processing time spent on such matters.

Claims

1. A memory device comprising:

memory locations adapted to store data;

first and second data input/output sections adapted to input data into the memory locations and to output data from the memory locations, wherein the first and second data input/output sections operate simultaneously; and

first and second data indication sections adapted to indicate a type of data being input into the memory locations, a type of data being output from the memory locations, an amount of data which can be input into the memory locations and an amount of data which can be output from the memory locations, wherein the first and second data indication sections operate simultaneously.

2. The device as in claim 1 wherein the first and second data input/output sections comprise first and second data input/output pins.

3. The device as in claim 1 wherein the first and second data indication sections comprise a first pair of data indication pins and a second pair of data indication pins.

4. The device as in claim 1 wherein the memory locations comprise first and second memory sections adapted to store data.

5. The device as in claim 4 wherein the first data input/output section is further adapted to input data into the first memory section and to output data from the second memory section and the second data input/output section is further adapted to input data into the second memory section and to output data from the first memory section, wherein the first and second data input/output sections operate simultaneously.

6. The device as in claim 4 wherein the first data indication section is further adapted to indicate a type of data being input into the first memory section, a type of data being output from the second memory section, an amount of data which can be input into subsections of the first memory section and an amount of data which can be output from subsections of the second memory section and the second data indication section is further adapted to indicate a type of data being input into the second memory section, a type of data being output from the first memory section, an amount of data which can be input to subsections of the second memory section and an amount of data which can be output from subsections of the first memory section, wherein the first and second data indication sections operate simultaneously.

7. The device as in claim 4 further comprising a plurality of memory pointers, wherein a first memory pointer is adapted to point to a next memory location in the first memory section where data can next be input, a second memory pointer is adapted to point to a next memory location in the first memory section where data can next be output, a third memory pointer is adapted to point to a next memory location in the second memory section where data can next be input and a fourth memory pointer is adapted to point to a next memory location in the second memory section where data can next be output.

8. The device as in claim 7 wherein the plurality of pointers is further adapted to point to a next memory location on a first input-first output basis.

9. The device as in claim 4 wherein the first data input/output section is further adapted to input data into the first memory section upon reception of a first mode signal and a write signal by the device and to output data from the second memory section upon reception of a first mode signal and a read signal by the device.

10. The device as in claim 4 wherein the second data input/output section is further adapted to input data into the second memory section upon reception of a first mode signal and a write signal by the device and to output data from the first memory section upon reception of a first mode signal and a read signal by the device.

11. The device as in claim 4 wherein the first data indication section is adapted to indicate the type of data being input into the first memory section upon reception of a first mode signal and a write signal by the device, the type of data being output from the second memory section upon reception of a first mode signal and a read signal by the device, the amount of data which can be input into subsections of the first memory section upon reception of a second mode signal and a write signal by the device and the amount of data which can be output from subsections of the second memory section upon reception of a second mode signal and a read signal by the device.

12. The device as in claim 4 wherein the second data indication section is adapted to indicate the type of data being input into the second memory section upon reception of a first mode signal and a write signal by the device, the type of data being output from the first memory section upon reception of a first mode signal and a read signal by the device, the amount of data which can be input into subsections of the second memory section upon reception of a second mode signal and a write signal by the device and the amount of data which can be output from subsections of the first memory section upon reception of a second mode signal and a read signal by the device.

13. The device as in claim 4 wherein the first data input/output section is further adapted to input data into the first memory section from a digital signal processor and to output data from the second memory section to the digital signal processor.

14. The device as in claim 4 wherein the second data input/output section is further adapted to input data into the second memory section from a microcontroller and to output data from the first memory section to the microcontroller.

15. The device as in claim 11 wherein the first data indication section is further adapted to indicate the type of data being input into the first memory section from a digital signal processor, the type of data being output from the second memory section to the digital signal processor, the amount of data which can be input into subsections of the first memory section by the digital signal processor and the amount of data which can be output from subsections of the second memory section to the digital signal processor.

16. The device as in claim 4 wherein the second data indication section is further adapted to indicate the type of data being input into the second memory section from a microcontroller, the type of data being output from the first memory section to the microcontroller, the amount of data which can be input to subsections of the second memory section from the microcontroller and the amount of data which can be output from subsections of the first memory section to the microcontroller.

17. The device as in claim 4 wherein the first and second memory sections comprise random access memory.

18. The device as in claim 4 wherein the first and second memory sections comprise static, random access memory.

19. The device as in claim 4 wherein the first data indication section is further adapted to input a pair of data bits indicating the type of data being input into the first memory section, to output a pair of data bits indicating the type of data being output from the second memory section, to output a pair of data bits indicating the amount of data which can be input into subsections of the first memory section and to output a pair of data bits indicating the amount of data which can be output from subsections of the second memory section.

20. The device as in claim 4 wherein the second data indication section is further adapted to input a pair of data bits indicating the type of data being input into the second memory section, to output a pair of data bits indicating the type of data being output from the first memory section, to output a pair of data bits indicating the amount of data which can be input to subsections of the second memory section and to output a pair of data bits indicating the amount of data which can be output from subsections of the first memory section.

21. The device as in claim 4 wherein the first memory section comprises an array of 64, 8 data bit locations.

22. The device as in claim 4 wherein the second memory section comprises an array of 64, 8 data bit locations.

23. The device as in claim 8 wherein the first and second data input/output sections comprise a dual port access to the memory device.

24. The device as in claim 1 wherein the first data input/output section comprises a serial data input/output section.

25. The device as in claim 1 wherein the first data input/output section comprises a parallel data input/output section.

26. The device as in claim 1 wherein the second data input/output section comprises a serial data input/output section.

27. The device as in claim 1 wherein the second data input/output section comprises a parallel data input/output section.

28. The device as in claim 1 wherein the device comprises part of a microcontroller.

29. The device as in claim 1 wherein the device comprises part of a digital signal processor.

30. The device as in claim 1 wherein the memory locations comprise an array of 128, 8 data bit locations.

31. A memory device comprising:

memory means for storing data;

first and second data input/output means for inputting data into the memory means and for outputting data from the memory means, wherein the first and second data input/output means operate simultaneously; and

first and second data indication means for indicating a type of data being input into the memory means, a type of data being output from the memory means, an amount of data which can be input into the memory means and an amount of data which can be output from the memory means, wherein the first and second data indication means operate simultaneously.

32. The device as in claim 31 wherein the first and second data input/output means comprise first and second data input/output pins.

33. The device as in claim 31 wherein the first and second data indication means comprise a first pair of data indication pins and a second pair of data indication pins.

34. The device as in claim 31 wherein the memory means comprises first and second memory means for storing data.

35. The device as in claim 34 wherein the first data input/output means is further adapted to input data into the first memory means and to output data from the second memory means and the second data input/output means is further adapted to input data into the second memory means and to output data from the first memory means, wherein the first and second data input/output means operate simultaneously.

36. The device as in claim 34 wherein the first data indication means is further adapted to indicate a type of data being input into the first memory means, a type of data being output from the second memory means, an amount of data which can be input into subsections of the first memory means and an amount of data which can be output from subsections of the second memory means and the second data indication means is further adapted to indicate a type of data being input into the second memory means, a type of data being output from the first memory means, an amount of data which can be input to subsections of the second memory means and an amount of data which can be output from subsections of the first memory means, wherein the first and second data indication means operate simultaneously.

37. The device as in claim 34 further comprising memory pointer means, the memory pointer means further comprising first memory pointer means for pointing to a next memory location in the first memory means where data can next be input, second memory pointer means for pointing to a next memory location in the first memory means where data can next be output, third memory pointer means for pointing to a next memory location in the second memory means where data can next be input and fourth memory pointer means for pointing to a next memory location in the second memory means where data can next be output.

38. The device as in claim 37 wherein the memory pointer means is further adapted to point to a next memory location on a first input-first output basis.

39. The device as in claim 34 wherein the first data input/output means is further adapted to input data into the first memory means upon reception of a first mode signal and a write signal by the device and to output data from the second memory means upon reception of a first mode signal and a read signal by the device.

40. The device as in claim 34 wherein the second data input/output section is further adapted to input data into the second memory means upon reception of a first mode signal and a write signal by the device and to output data from the first memory means upon reception of a first mode signal and a read signal by the device.

41. The device as in claim 34 wherein the first data indication means is adapted to indicate the type of data being input into the first memory means upon reception of a first mode signal and a write signal by the device, the type of data being output from the second memory means upon reception of a first mode signal and a read signal by the device, the amount of data which can be input into subsections of the first memory means upon reception of a second mode signal and a write signal by the device and the amount of data which can be output from subsections of the second memory means upon reception of a second mode signal and a read signal by the device.

42. The device as in claim 34 wherein the second data indication means is adapted to indicate the type of data being input into the second memory means upon reception of a first mode signal and a write signal by the device, the type of data being output from the first memory means upon reception of a first mode signal and a read signal by the device, the amount of data which can be input into subsections of the second memory means upon reception of a second mode signal and a write signal by the device and the amount of data which can be output from subsections of the first memory means upon reception of a second mode signal and a read signal by the device.

43. The device as in claim 34 wherein the first data input/output section is further adapted to input data into the first memory means from a digital signal processor and to output data from the second memory means to the digital signal processor.

44. The device as in claim 34 wherein the second data input/output means is further adapted to input data into the second memory means from a microcontroller and to output data from the first memory means to the microcontroller.

45. The device as in claim 41 wherein the first data indication means is further adapted to indicate the type of data being input into the first memory means from a digital signal processor, the type of data being output from the second memory means to the digital signal processor, the amount of data which can be input into subsections of the first memory means by the digital signal processor and the amount of data which can be output from subsections of the second memory means to the digital processor.

46. The device as in claim 34 wherein the second data indication means is further adapted to indicate the type of data being input into the second memory means from a microcontroller, the type of data being output from the first memory means to the microcontroller, the amount of data which can be input to subsections of the second memory means from the microcontroller and the amount of data which can be output from subsections of the first memory means to the microcontroller.

47. The device as in claim 34 wherein the first and second memory means comprise random access memory.

48. The device as in claim 34 wherein the first and second memory means comprise static, random access memory.

49. The device as in claim 34 wherein the first data indication means is further adapted to input a pair of data bits indicating the type of data being input into the first memory means, to output a pair of data bits indicating the type of data being output from the second memory means, to output a pair of data bits indicating the amount of data which can be input into subsections of the first memory means and to output a pair of data bits indicating the amount of data which can be output from subsections of the second memory means.

50. The device as in claim 34 wherein the second data indication means is further adapts to input a pair of data bits indicating the type of data being input into the second memory means, to output a pair of data bits indicating the type of data being output from the first memory means, to output a pair of data bits indicating the amount of data which can be input to subsections of the second memory means and to output a pair of data bits indicating the amount of data which can be output from subsections of the first memory means.

51. The device as in claim 34 wherein the first memory means comprises an array of 64, 8 data bit locations.

52. The device as in claim 34 wherein the second memory means comprises an array of 64, 8 data bit locations.

53. The device as in claim 31 wherein the first and second data input/output means comprise a dual port access to the memory device.

54. The device as in claim 31 wherein the first data input/output means comprises a serial data input/output section.

55. The device as in claim 31 wherein the first data input/output means comprises a parallel data input/output section.

56. The device as in claim 31 wherein the second data input/output means comprises a serial data input/output section.

57. The device as in claim 31 wherein the second data input/output means comprises a parallel data input/output section.

58. The device as in claim 31 wherein the device comprises part of a microcontroller.

59. The device as in claim 31 wherein the device comprises part of a digital signal processor.

60. The device as in claim 31 wherein the memory means comprises an array of 128, 8 data bit locations.