Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entries

• US 6,289,431 B1
• Filed: 01/26/1998
• Issued: 09/11/2001
• Est. Priority Date: 01/26/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hacking, Lance E., Thakkar, Shreekant S., Shahidzadeh, Shahrokh, Bigbee, Bryant E.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/013,414
• Time in Patent Office: 1,324 Days
• Field of Search: 711/203, 711/206, 711/207, 711/170, 711/171, 711/172, 711/173
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures

Abstract

A method and apparatus for accessing pages in physical memory, where the physical memory is described. The present invention provides a paged memory system having multiple page sizes. Pages of a first size are accessed via a page directory entry and a corresponding page table entry. The page directory entry stores a base physical address for a corresponding page table and control bits indicating permissions. The page table entry stores a base physical address of the page in memory. In one embodiment, the page table entry inherits permissions from the page directory entry. Pages of a second size are accessed via a page directory entry that stores a base physical address of the page and control bits indicating permissions associated with the page. In another embodiment, entries to the page directory table and the page table are 4-bytes in size and provide paging for memory up to 1.1 Terabytes in size.

Claims

1. A system comprising:

a bus;

a memory coupled to the bus, wherein the memory is addressed as paged memory having a first page size and a second page size, and further wherein the memory is greater than 4 Megabytes in size;

a plurality of page directory tables stored in the memory, each page directory table having a plurality of 4-byte entries storing a base address and control bits indicating permissions;

a plurality of page tables stored in the memory, each page table having a plurality of 4-byte entries and corresponding to one of the plurality of base addresses, wherein each page table entry stores a base address of a page stored in memory; and

a processor coupled to the bus, wherein the processor accesses pages in the memory of the first page size, the processor accesses one of the plurality of page directory entries and one of the plurality of page table entries to access a base address for the page of the first page size, wherein the page table entry inherits permissions from the page directory entry, and wherein the processor accesses pages in memory of the second page size, the processor accesses one of the plurality of page directory entries to retrieve a base address for the page of the second page size.

2. The system of claim 1, wherein the memory pages of the first size are 4 kilobytes in size.

3. The system of claim 1, wherein the memory pages of the second size are 4 Megabytes.

4. The system of claim 3, wherein the memory pages of the second size have addresses less than 4 Gigabytes.

5. A method for accessing paged memory comprising:

decoding a linear address;

accessing a page directory table entry that provides a base address in response to decoding the linear address;

if the page directory table entry corresponds to a first page of a first predetermined size, then

accessing a page table having a page table base address corresponding to the base address, wherein the page table has an entry that inherits permissions from the page directory table entry and provides a first page base address of the first page, and

accessing a physical address in the first page corresponding to the linear address;

if the page directory table entry corresponds to a second page of a second predetermined size, then

accessing a second physical address in the second page, wherein the second page has a second page base address corresponding to the base address in the page directory entry, and further wherein the second physical address corresponds to the linear address.

6. The method of claim 5, wherein the first predetermined size is 4 kilobytes.

7. The method of claim 5, wherein the second predetermined size is 4 Megabytes.

8. The method of claim 5, wherein the pages of the first predetermined size have base page addresses less than 4 Gigabytes.

9. The method of claim 5, wherein the memory is greater than 4 Gigabytes in size.

10. The method of claim 5, wherein the page directory table entry and the page table entry are 4-byte entries.

11. The method of claim 5, wherein accessing a page directory entry further comprises:

determining a base address of a page directory;

determining an offset from the base address of the page directory based on directory bits of the linear address; and

accessing the page directory entry having a base address of a corresponding page table based on an offset from the base address of the page directory table.

12. The method of claim 5, wherein accessing a physical address in the first page further comprises:

determining a base address of a page table based on the page directory entry;

determining an offset from the base address of the page table based on table bits of the linear address; and

accessing a page table entry having a base address of the first page.

13. The method of claim 5, wherein accessing a physical address in the first page further comprises:

determining a base address of the first page based on a page table entry;

determining an offset from the base address of the first page based on offset bits of the linear address; and

accessing the physical address corresponding to the linear address.

14. A system comprising:

a bus;

a memory coupled to the bus; and

a processor coupled to the bus, wherein the processor accesses the memory via a paging system having two page sizes, further wherein pages of one of the two page sizes are accessed by a page directory entry and a page table entry where the page table entry inherits permissions from the page directory entry.

15. The system of claim 14, wherein the memory is greater than 4 Gigabytes in size.

16. The system of claim 14, wherein the page directory entry and the page table entry are 4-bytes in size.

17. The system of claim 14, wherein the memory comprises a first portion and a second portion, the first portion of memory comprises memory locations up to 4 Gigabytes.

18. The system of claim 14, wherein the memory comprises a first portion and a second portion, the second portion of memory comprises memory locations above 4 Gigabytes.

19. The system of claim 14, wherein the memory comprises a first portion and a second portion, the first portion of memory comprises a plurality of 4-kilobyte pages and a plurality of 4-Megabyte pages.

20. The system of claim 14, wherein the memory comprises a first portion and a second portion, the second portion of memory comprises a plurality of 4-Megabyte pages.

21. The system of claim 17, wherein pages in the first portion of memory are accessed by the processor accessing a first page directory entry having a base address of a corresponding page table, accessing a base address of a corresponding page in the first portion of memory from an entry in the page table, and accessing a physical address in the corresponding page in the first portion of memory corresponding to a linear address.

22. The system of claim 18, wherein pages in the second portion of memory are accessed by the processor accessing a page directory entry having a base address of a corresponding page in the second portion of memory, and accessing a physical address in the corresponding page in the second poriton of memory corresponding to a linear address.