Data processing apparatus for IC tester

• US 6,289,478 B1
• Filed: 02/20/1999
• Issued: 09/11/2001
• Est. Priority Date: 02/27/1998
• Status: Expired due to Fees

• Current Assignee: Verigy Limited (Advantest Corporation)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Kitagaki, Takashi
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US09/253,654
• Time in Patent Office: 934 Days
• Field of Search: 714/724, 714/738, 714/739, 714/32, 714/33, 703/13, 703/14, 703/15, 703/21, 703/23, 703/24, 703/25, 703/28
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

A data processing apparatus for an IC tester that generates data or evaluates data, includes a first memory; a first reconfigurable logic device operative during input and output of data, for converting signals for internal use in the data processing apparatus, an internal configuration of the first reconfigurable logic device being alterable to accomplish such converting; a second reconfigurable logic device for receiving data from the first memory or the first reconfigurable logic device and for processing the data in accordance with an internally configured combination of elements, an internal configuration of the second reconfigurable logic device being alterable to accomplish details of the processing; a third reconfigurable logic device for establishing a specific interface when data is transmitted and received between the second reconfigurable logic device and the first memory, an internal configuration of the third reconfigurable logic device being alterable in accordance with a selected type of interface; and a device coupled to each of the first, second and third reconfigurable logic devices for inputting an internal configuration to each thereof.

Claims

1. A data processing apparatus for an integrated circuit (IC) tester, comprising:

a first memory;

a first reconfigurable logic device operative during input and output of data therefrom and thereto, for outputting signals used for generating test vectors for an IC, and for receiving and converting data derived from the IC for internal use in said data processing apparatus, an internal configuration of the first reconfigurable logic device being alterable to accomplish such converting;

a second reconfigurable logic device for receiving data from, and transmitting data to, the first memory or the first reconfigurable logic device and for processing the data in accordance with an internally configured combination of elements therein, an internal configuration of the second reconfigurable logic device being alterable to accomplish details of said processing of said data;

a third reconfigurable logic device for establishing a specific interface when data is transmitted and received between the second reconfigurable logic device and the first memory, an internal configuration of the third reconfigurable logic device being alterable in accordance with a selected type of interface with the first memory; and

writing means coupled to each of said first, second and third reconfigurable logic devices for inputting an internal configuration to each thereof.

2. The data processing apparatus in claim 1, further comprising:

a second memory for transmitting data to and receiving data from the second reconfigurable logic device; and

a high speed bus for providing a path for transmission and reception of data between the second memory and the second reconfigurable logic device, said path different from a path for data between the second and third reconfigurable logic devices.

3. The data processing apparatus in claim 2, further comprising:

a digital signal processor for transmitting data to and receiving data from the second memory and for sending data to and receiving data from the second and third reconfigurable logic devices.

4. The data processing apparatus as recited in claim 3, further comprising:

a control part for controlling the first through third configurable logic devices and the digital signal processor.

5. The data processing apparatus as recited in claim 4, wherein the control part comprises a sequencer and a sequence memory.

6. The data processing apparatus as recited in claim 1, wherein said first, second and third reconfigurable logic devices comprise field programmable gate arrays (FPGAs).