Method and apparatus for local optimization of the global routing

• US 6,289,495 B1
• Filed: 04/17/1998
• Issued: 09/11/2001
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, Andreev, Alexander E., Raspopovic, Pedja
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/062,205
• Time in Patent Office: 1,243 Days
• Field of Search: 716/12
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for routing nets in an integrated circuit design, said method comprising the steps of forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction, globally routing said integrated circuit design in accordance with said routing graph, dividing the routing graph into strips, for each strip in the routing graph, generating a general task for optimizing the routing in the strip, solving general tasks in parallel by assigning different processors different strips to process.

Claims

1. A method for routing nets in an integrated circuit design, said method comprising the following steps:

a. Forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction;

b. globally routing said integrated circuit design in accordance with said routing graph;

c. dividing the routing graph into strips;

d. for each strip in the routing graph, generating a general task for optimizing the routing in the strip;

e. solving general tasks in parallel by assigning different processors different strips to process.

2. The method of claim 1 wherein general tasks are generated with respect to each net fragment which passes in a strip.

3. The method of claim 2 wherein the solving of general tasks is repeated for a predetermined number of times with respect to a particular strip.

4. The method of claim 1 wherein an edge in the routing graph has an associated penalty and the solution of a general task is a function of the penalty.

5. The method of claim 4 wherein the penalty is a function of an occupancy value and a capacity value associated with the edge.

6. The method of claim 4 wherein the solving of a general task involves determining a vector of minimal penalty.

7. The method of claim 1 wherein a second routing graph is formed, nets are rerouted in accordance with the second routing graph, and steps c, d and e are repeated with respect to said second routing graph.

8. The method of claim 1 wherein a strip comprises a small number of lines comprising edges in the first direction and edges in the second direction connecting said lines.

9. The method of claim 1, wherein at least one of said strips includes more than one pin from a net.

10. A apparatus for routing nets in an integrated circuit design, said apparatus comprising:

a. means for forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction;

b. means for globally routing said integrated circuit design in accordance with said routing graph;

c. means for dividing the routing graph into strips;

d. means for, for each strip in the routing graph, generating a general task for optimizing the routing in the strip;

e. means for solving general tasks in parallel by assigning different processors different strips to process.

11. The apparatus of claim 10 wherein general tasks are generated with respect to each net fragment which passes in a strip.

12. The apparatus of claim 11 wherein the solving of general tasks is repeated for a predetermined number of times with respect to a particular strip.

13. The apparatus of claim 10 wherein an edge in the routing graph has an associated penalty and the solution of a general task is a function of the penalty.

14. The apparatus of claim 13 wherein the penalty is a function of an occupancy value and a capacity value associated with the edge.

15. The apparatus of claim 13 wherein the solving of a general task involves determining a vector of minimal penalty.

16. The apparatus of claim 10 further comprising means for forming a second routing graph, means for rerouting nets in accordance with the second routing graph, and means for reutilizing elements c, d and e with respect to said second routing graph.

17. The apparatus of claim 10 wherein a strip comprises a small number of lines comprising edges in the first direction and edges in the second direction connecting said lines.

18. The apparatus of claim 10, wherein at least one of said strips includes more than one pin from a net.

19. A computer encoded storage medium with instructions thereon for routing nets in an integrated circuit design, said storage medium comprising:

a. a computer encoded instruction for forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction;

b. a computer encoded instruction for globally routing said integrated circuit design in accordance with said routing graph;

c. a computer encoded instruction for dividing the routing graph into strips;

d. a computer encoded instruction for for each strip in the routing graph, generating a general task for optimizing the routing in the strip;

e. a computer encoded instruction for solving general tasks in parallel by assigning different processors different strips to process.

20. The storage medium of claim 19, wherein at least one of said strips includes more than one pin from a net.