CMOS imager cell having a buried contact and method of fabrication

• US 6,291,280 B1
• Filed: 12/09/1999
• Issued: 09/18/2001
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/457,264
• Time in Patent Office: 649 Days
• Field of Search: 438/57, 438/91, 438/200, 438/199, 438/231, 438/526, 257/291, 257/292
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823406 Combination of charge coupled devices, i.e. CCD, or BBD
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact between the floating diffusion region and the gate of a source follower output transistor. The buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a buried contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region on, thereby allowing a greater photo detection region in the same sized imager circuit.

Claims

1. A method of forming a buried contact line between a diffusion node and an output transistor in a CMOS imager, comprising:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate which functions as said diffusion node;

forming an isolation region in said substrate;

forming an insulating layer over said substrate, wherein said insulating layer is formed over at least a part of said diffusion region;

selectively removing at least a portion of said insulating layer to form a diffusion contact area over said diffusion region;

forming in output transistor on said substrate;

forming a continuously conductive layer directly on at least a portion of said isolation region to connect said diffusion contact area and a gate of said output transistor, wherein a buried contact between said conductive layer and said diffusion region is formed by diffusion of dopants from said conductive layer into said diffusion region.

2. The method according to claim 1, wherein said insulating layer is silicon dioxide.

3. The method according to claim 1, wherein said conductive layer is doped polysilicon.

4. The method according to claim 3, wherein said diffusion region is n-doped.

5. The method according to claim 3, further comprising forming a silicide layer over said polysilicon conductive layer.

6. The method according to claim 1, wherein said first conductivity type is p-type and said second conductivity type is n-type.

7. A method according to claim 1, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

8. The method according to claim 1, wherein said insulating layer is removed to form said diffusion contact area over said diffusion region by etching.

9. A method of forming a buried contact fine between a floating diffusion node and a source follower transistor in a CMOS imager, comprising

providing a semiconductor substrate doped to a first conductivity;

forming a floating diffusion region of a second conductivity in said substrate;

forming an insulating layer of silicon dioxide over at least a portion of said substrate, wherein said insulating layer is formed over at least said floating diffusion region;

selectively etching at least a portion of said insulating layer to form a floating diffusion contact region over said diffusion region;

forming a source follower transistor adjacent to said floating diffusion region; and

forming a doped polysilicon layer on at least a portion of said insulating layer to connect said floating diffusion contact and said source follower transistor gate, wherein a buried contact between said doped polysilicon layer and said floating diffusion region is formed by diffusion of dopants from said doped polysilicon layer into said diffusion region.

10. The method according to claim 9, wherein said floating diffusion region is n-doped.

11. A method of forming a buried contact line between a diffusion node and an output transistor in a CMOS imager, comprising:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate which functions as said diffusion node;

forming an isolation region in said substrate;

forming an insulating layer of silicon dioxide over at least a portion of said substrate, wherein said insulating layer is formed over at least said diffusion region;

selectively removing at least a portion of said insulating layer to form a diffusion contact area over said diffusion region;

forming an output transistor area on said substrate;

forming a continuously conductive layer directly on at least a portion of said isolation region to connect said diffusion contact area wherein said continuously conductive layer functions as a gate for the output transistor;

forming a buried contact between said conductive layer and said diffusion region by diffusion of dopants from said conductive layer into said diffusion region; and

removing a part of said conductive layer to form the connection between said diffusion contact and a gate of said output transistor.

12. The method according to claim 11, wherein said insulating layer is silicon dioxide.

13. The method according to claim 11, wherein said conductive layer is doped polysilicon.

14. The method according to claim 13, further comprising forming a silicide layer over said polysilicon conductive layer.

15. The method according to claim 11, wherein said first conductivity type is p-type and said second conductivity type is n-type.

16. The method according to claim 11, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

17. The method according to claim 11, wherein said insulating layer is removed to form said diffusion contact area over said diffusion region by etching.

18. The method according to claim 11, wherein said conductive layer is patterned and etched to form the connection between said diffusion contact area over said output transistor gate.

19. A method of forming a buried contact line between a diffusion node and an output transistor in a CMOS imager aligned at a field oxide edge, comprising:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate which functions as said diffusion node;

forming an output transistor on said substrate;

forming field oxide region adjacent to said diffusion region in said substrate to isolate said output transistor;

forming an insulating layer of silicon dioxide over at least a portion of said substrate, wherein said insulating layer is formed over at least said diffusion region;

providing a mask and resist over said substrate and selectively removing said insulating layer adjacent said field oxide region to form a diffusion contact area over said diffusion region;

forming a continuously conductive layer directly over on at least a portion of said field oxide region to connect said diffusion contact area and a gate of said output transistor wherein a buried contact is formed by diffusion of dopants from said conductive layer into said diffusion region; and

removing a part of said conductive layer to form the connection between said diffusion contact and said gate of said output transistor.

20. The method according to claim 19, wherein said insulating layer is silicon dioxide.

21. The method according to claim 19, wherein said conductive layer is doped polysilicon.

22. The method according to claim 21, further comprising forming a silicide layer over said doped polysilicon conductive layer.

23. The method according to claim 19, wherein said first conductivity type is p-type and said second conductivity type is n-type.

24. The method according to claim 19, wherein said insulating layer is removed to form said diffusion contact area over said diffusion region by etching.

25. The method according to claim 19, wherein said conductive layer is patterned and etched to form the connection between said diffusion contact area over said output transistor gate.

26. The method according to claim 19, wherein said conductive layer also functions as the gate for said output transistor.

27. The method according to claim 19, wherein said output transistor is a source follower transistor.