Flash memory cell with self-aligned gates and fabrication process

• US 6,291,297 B1
• Filed: 10/26/1999
• Issued: 09/18/2001
• Est. Priority Date: 03/24/1999
• Status: Expired due to Term

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Actrans Systems Inc. (Microchip Technology Incorporated)
• Inventors: Chen, Chiou-Feng
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/427,885
• Time in Patent Office: 693 Days
• Field of Search: 438/257, 438/265, 438/266, 438/267, 438/304, 438/593, 438/594, 438/596
• US Class Current: 438/265
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Nonvolatile memory cell and process in which a control gate or a thick dielectric film is used as a mask in the formation of a floating gate and also as a step in the formation and alignment of a select gate. The floating gate is relatively thin and has a side wall with a rounded curvature which, in some embodiments, serves as a tunneling window for electrons migrating to the select gate during erase operations. In other embodiments, the gate oxide beneath the floating gate is relatively thin, and the electrons tunnel through the gate oxide to the source region in the substrate below.

Claims

1. In a process of fabricating a semiconductor device having a floating gate, a control gate and a select gate, the steps of:

forming an oxide layer in an active area on a silicon substrate;

forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

etching away a portion of the second silicon layer to form a control gate;

using the control gate as a mask, anisotropically etching away portions of the dielectric film and the first silicon layer to form a floating gate beneath the control gate;

forming a third silicon layer over the substrate and the control gate with a step in the third silicon layer beside and above the control gate; and

anisotropically etching the third silicon layer to form a select gate beside the control gate.

2. The process of claim 1 wherein the thickness of the third silicon layer is less than the total thickness of the layers beneath it where it steps over the control gate.

3. The process of claim 1 further including the step of forming a rounded curvature on a side wall of the floating gate.

4. The process of claim 3 wherein the rounded curvature is formed by oxidation of the side wall, with the oxidation occurring at a greater rate near the oxide layer beneath the floating gate and near the dielectric film above it.

5. The process of claim 1 wherein the dielectric film is formed by forming a bottom oxide layer on the first silicon layer, forming a nitride layer on the bottom oxide layer, and forming a top oxide layer on the nitride layer.

8. The process of claim 1 wherein the oxide layer is formed with a thickness on the order of 70-250 Å

, the first silicon layer is formed with a thickness on the order of 100-1000 Å

, the dielectric film is formed with a thickness on the order of 120-500 Å

, the second silicon layer is formed with a thickness on the order of 1500-3500 Å

, and the third silicon layer is formed with a thickness on the order 2000-4000 Å

.

9. The process of claim 1 including the steps of doping each of the silicon layers with a dopant selected from the group consisting of phosphorus, arsenic and boron.

10. The process of claim 1 wherein the first silicon layer is doped to a level on the order of 10¹⁷ to 10²⁰ per cm³.

11. The process of claim 1 wherein the second and third silicon layers are doped to a level on the order of 10²⁰ to 10²¹ per cm³.

6. In a process of fabricating a semiconductor device having a floating gate, a control gate and a select gate, the steps of:

forming an oxide layer in an active area on a silicon substrate;

forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

etching away a portion of the second silicon layer to form a control gate;

using the control gate as a mask, anisotropically etching away portions of the dielectric film and the first silicon layer to form a floating gate beneath the control gate;

forming a third silicon layer over the substrate and the control gate with a step in the third silicon layer beside and above the control gate;

anisotropically etching the third silicon layer to form a select gate beside the control gate;

forming a nitride layer on the third silicon layer; and

anisotropically removing the nitride everywhere except in a shoulder area of the step in the third silicon layer.

7. In a process of fabricating a semiconductor device having a floating gate, a control gate and a select gate, the steps of:

forming an oxide layer in an active area on a silicon substrate;

forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

etching away a portion of the second silicon layer to form a control gate;

using the control gate as a mask, anisotropically etching away portions of the dielectric film and the first silicon layer to form a floating gate beneath the control gate;

forming a third silicon layer over the substrate and the control gate with a step in the third silicon layer beside and above the control gate;

anisotropically etching the third silicon layer to form a select gate beside the control gate;

forming an additional oxide layer on the third silicon layer; and

anisotropically removing the additional layer everywhere except in a shoulder area of the step in the third silicon layer.

12. In a process of fabricating a semiconductor device, the steps of:

forming an oxide layer in an active area on a silicon substrate;

forming a first silicon layer on the oxide layer;

forming a relatively thick dielectric film above the first silicon layer;

anisotropically etching the relatively thick dielectric film to form a step above the active area;

using the step as a mask, anisotropically etching the first silicon layer to form a floating gate above the active area;

forming a second silicon layer over the substrate and the step; and

anisotropically etching the second silicon layer to form a select gate beside the floating gate.

13. The process of claim 12 wherein the dielectric film is formed by forming a bottom oxide layer to a thickness on the order of 50-300 Å

thick, forming a nitride layer on the bottom oxide layer to a thickness on the order of 1000-2000 Å

thick, and forming a top oxide layer on the nitride layer to a thickness on the order of 200-1000 Å

.

14. The process of claim 12 wherein the dielectric film is formed by forming a bottom oxide layer on the first silicon layer to a thickness on the order of 50-300 Å

, and forming a nitride layer on the bottom oxide layer to a thickness on the order of 1000-3000 Å

.

15. The process of claim 12 wherein the thickness of the second silicon layer is less than the height of the step.

16. The process of claim 12 further including the step of forming a rounded curvature on a side wall of the floating gate.

17. The process of claim 16 wherein the rounded curvature is formed by oxidation of the side wall, with the oxidation occurring at a greater rate near the oxide layer beneath the floating gate and near the dielectric film above it.

18. In a process of fabricating a semiconductor device, the steps of:

forming an oxide layer in an active area on a silicon substrate;

forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

forming a dielectric film on the second silicon layer;

etching away a portion of the second silicon layer and the dielectric film on it to form a control gate;

forming a thermal oxide on side walls of the control gate;

using the control gate and the oxide on its side walls as a mask, anisotropically etching away portions of the dielectric film and the first silicon layer to form a floating gate beneath the control gate, with edge portions of the floating gate projecting beyond the side walls of the control gate;

forming a rounded curvature on the side walls of the projecting portions of the floating gate by thermal oxidation;

forming a third silicon layer over the substrate and the control gate with a step in the third silicon layer beside and above the control gate; and

anisotropically etching the third silicon layer to form a select gate which is self-aligned with the control gate and the floating gate.

19. In a process of fabricating a semiconductor device, the steps of:

forming an oxide layer in an active area on a silicon substrate;

forming a first silicon layer on the oxide layer;

forming a relatively thick dielectric film above the first silicon layer;

anisotropically etching the relatively thick dielectric film to form a step above the active area;

using the step as a mask, anisotropically etching the first silicon layer to form a floating gate above the active area;

forming a rounded curvature on the side wall of the floating gate by thermal oxidation;

forming a second silicon layer over the substrate and the step; and

anisotropically etching the second silicon layer to form a select gate which is self-aligned to the floating gate.