Process of manufacturing Trench gate semiconductor device having gate oxide layer with multiple thicknesses

• US 6,291,298 B1
• Filed: 05/25/1999
• Issued: 09/18/2001
• Est. Priority Date: 05/25/1999
• Status: Expired due to Term

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne B.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): LEE, HSIEN MING
• Application Number:
  US09/318,403
• Time in Patent Office: 847 Days
• Field of Search: 438/270, 438/269, 438/268, 438/271, 438/272, 438/273, 438/274, 438/206, 438/212, 257/330, 257/333
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

Claims

1. A process of manufacturing a trench gate semiconductor device comprising:

providing a semiconductor material;

forming a trench at a surface of the semiconductor material;

placing the semiconductor material in a reaction chamber;

producing charged particles of a dielectric within the chamber;

creating an electric field in the reaction chamber, the electric field causing the charged particles to move towards the semiconductor material such that the dielectric is deposited at a greater thickness on a bottom of the trench than on a sidewall of the trench;

depositing a conductive material in the trench to form a gate electrode; and

removing the dielectric from the sidewall of the trench.

2. The process of claim 1 wherein removing the dielectric comprises etching.

3. The process of claim 1 comprising, after removing the dielectric, heating the semiconductor material to form a thin oxide layer on the sidewall of the trench.

4. The process of claim 3 wherein depositing a conductive material in the trench comprises filling the trench with a first polysilicon layer.

5. The process of claim 4 comprising removing a portion of the first polysilicon layer such that a surface of the first polysilicon layer is approximately coplanar with the surface of the semiconductor material.

6. The process of claim 5 comprising oxidizing the first polysilicon layer to form a second oxide layer.

7. The process of claim 6 comprising depositing a glass layer on the second oxide layer.

8. The process of claim 4 comprising removing a portion of the first polysilicon layer such that a surface of the first polysilicon layer is at a level below the surface of the semiconductor material.

9. The process of claim 8 comprising oxidizing the first polysilicon layer to form a second oxide layer.

10. The process of claim 9 comprising depositing a glass layer on the second oxide layer.

11. The process of claim 8 comprising depositing a second polysilicon layer on the first polysilicon layer, the second polysilicon layer covering a portion of the thin oxide layer at an upper corner of the trench.

12. The process of claim 11 comprising removing a portion of the second polysilicon layer while leaving the second polysilicon layer covering the portion of the thin oxide layer at the upper corner of the trench.

13. The process of claim 12 comprising forming a second oxide layer over the second polysilicon layer.

14. The process of claim 4 comprising depositing a photoresist layer over the dielectric.

15. The process of claim 14 comprising removing a first portion of the photoresist layer while leaving a second portion of the photoresist layer overlying the dielectric at the bottom of the trench before removing the dielectric from the sidewall of the trench.

16. The process of claim 4 comprising removing a portion of the first polysilicon layer such that a surface of the first polysilicon layer is at a level above the surface of the semiconductor material.

17. The process of claim 16 comprising oxidizing the first polysilicon layer to form a second oxide layer.

18. The process of claim 17 wherein after oxidizing the first polysilicon layer the second oxide layer extends from a level above the surface of the semiconductor material into the trench.

19. A process of manufacturing a trench gate semiconductor device comprising:

providing a semiconductor material;

forming a trench at a surface of the semiconductor material;

placing the semiconductor material in a reaction chamber;

producing charged particles of a dielectric within the chamber;

creating an electric field in the reaction chamber, the electric field causing the charged particles to move towards the semiconductor material such that the dielectric is deposited at a greater thickness on a bottom of the trench than on a sidewall of the trench;

depositing a conductive material in the trench to form a gate electrode; and

forming a second trench in the semiconductor material, wherein the electric field causes the charged particles to move towards the semiconductor material such that the dielectric is deposited at a greater thickness on a bottom of the second trench than on a sidewall of the second trench.

20. The process of claim 19 wherein depositing the conductive material comprises depositing polysilicon such that the polysilicon fills both the first and second trenches and overlies the semiconductor material between the first and second trenches.

21. The process of claim 20 comprising depositing a hard layer over the polysilicon in the area of the second trench.

22. The process of claim 21 comprising etching a portion of the polysilicon in the area of the first trench, the hard layer acting as a mask layer in the area of the second trench, the etching forming an exposed edge of the polysilicon between the areas of the first and second trenches.

23. The process of claim 22 comprising heating the polysilicon so as to form an oxide layer in the area of the first trench.

24. The process of claim 23 wherein the heating forms a second oxide layer in the exposed edge of the polysilicon, the polysilicon in the area of the second trench forming a gate bus.

25. A process of manufacturing a trench gate semiconductor device comprising:

providing a semiconductor material;

forming a trench at a surface of the semiconductor material;

placing the semiconductor material in a reaction chamber;

producing charged particles of a dielectric within the chamber;

creating an electric field in the reaction chamber, the electric field causing the charmed particles to move towards the semiconductor material such that the dielectric is deposited at a greater thickness on a bottom of the trench than on a sidewall of the trench;

depositing a conductive material in the trench to form a gate electrode;

and further comprising, before forming the trench;

depositing at least one layer on the surface of the semiconductor materal, the at least one layer comprising a hard layer;

removing a portion of the at least one layer to expose an area of the surface of the semiconductor material, leaving exposed edges of the at least one layer;

depositing a nitride layer, the nitride layer covering the at least one hard layer, the exposed area of the surface of the semiconductor material, and the exposed edges of the at least one hard layer; and

etching the nitride layer anisotropically so as to remove the nitride layer from a top surface of the at least one hard layer and a portion of the exposed area of the surface of the semiconductor material while leaving a portion of the nitride layer covering the exposed edges of the at least one hard layer.

26. The process of claim 25 wherein depositing the at least one hard layer comprises depositing a second nitride layer.

27. The process of claim 26 wherein depositing the at least one hard layer comprises depositing an oxide-nitride-oxide sandwich.