Semiconductor device with alternating conductivity type layer and method of manufacturing the same

• US 6,291,856 B1
• Filed: 11/10/1999
• Issued: 09/18/2001
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Iwamoto, Susumu, Ueno, Katsunori, Miyasaka, Yasushi, Fujihira, Tatsuhiko, Ohnishi, Yasuhiko
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US09/438,078
• Time in Patent Office: 678 Days
• Field of Search: 257/335, 257/336, 257/337, 257/341, 257/342
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

Claims

1. A super-junction semiconductor device comprising:

first and second principal faces;

first and second principal electrodes provided on at least one of said first and second principal faces; and

a parallel pn layer, in which first-conductivity-type drift regions and second-conductivity-type partition regions are arranged alternately, said parallel pn layer being provided between the first and second principal faces of a substrate;

wherein the quantity of impurities in said first-conductivity-type drift regions is greater than the quantity of impurities in said second-conductivity-type partition regions.

2. A super-junction semiconductor device as claimed in claim 1, wherein the quantity of impurities in said first-conductivity-type drift regions is within the range between 110% and 150% of the quantity of impurities in said second-conductivity-type partition regions.

3. The super-junction semiconductor device as defined in claim 1, wherein both said conductive drift regions and said second-conductivity-type partition regions are arranged in stripes.

4. The super-junction semiconductor device as defined in claim 2, wherein both said conductive drift regions and said second-conductivity-type partition regions are arranged in stripes.

5. The super-junction semiconductor device as defined in claim 1, wherein said first and second principal electrodes are respectively provided on said first and second principal faces.

6. The super-junction semiconductor device as defined in claim 2, wherein said first and second principal electrodes are respectively provided on said first and second principal faces.