Method and apparatus for a semiconductor package for vertical surface mounting

• US 6,291,894 B1
• Filed: 08/31/1998
• Issued: 09/18/2001
• Est. Priority Date: 08/31/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsman, Larry, Farnworth, Warren, Moden, Walter
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/143,765
• Time in Patent Office: 1,114 Days
• Field of Search: 257/620, 257/786, 257/785, 257/784, 257/780, 438/612, 438/613, 438/617, 438/113, 438/110, 438/111, 438/460, 438/462, 361/767, 361/772, 361/760, 361/761, 361/729-736, 361/743, 361/679, 361/724, 361/727
• US Class Current: 257/780
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method for packaging a semiconductor device includes connecting a plurality of wire leads to a corresponding plurality of electrical connection pads on the semiconductor device, covering at least a portion of the semiconductor device and at least a portion of each of the wire leads with an encapsulating material, and removing a portion of the encapsulating material and a portion of each of the wire leads to form a packaged semiconductor device wherein each of the wire leads has an exposed portion only at an end. The invention also includes a packaged semiconductor device having an integrated circuit device with a plurality of electrical connection pads, a plurality of wire leads coupled to the plurality of electrical connection pads, and a covering of encapsulating material covering at least a portion of the integrated circuit device and covering each of the wire leads, wherein each of the wire leads has an exposed end. The present invention contemplates wire bonding and encapsulation of individual die as well as multiple die on a single wafer.

Claims

1. A processed semiconductor wafer, comprising:

a semiconductor wafer having first and second integrated circuit devices formed on a first surface of the wafer;

a first plurality of contact pads associated with the first integrated circuit device and a second plurality of contact pads associated with the second integrated circuit device;

a plurality of wire leads coupled between the first and second pluralities of contact pads;

a covering of encapsulating material substantially covering at least the first and second integrated circuit devices, covering the first and second pluralities of contact pads, and covering the wire leads coupled between the first and second integrated circuit devices; and

a scribe line between the first plurality of contact pads and the second plurality of contact pads, the scribe line extending orthogonally to the wire leads and defining a boundary along which the first integrated circuit device and the second integrated circuit device are to be separated, whereby, upon separation of the first and second integrated circuit devices, each of the first and second integrated circuit devices includes a plurality of exposed ends of wire leads for electrical contact along only an edge surface, the exposed ends being substantially flush with the edge surface.

2. The wafer of claim 1, wherein the covering of encapsulating material is deposited on at least two surfaces of the semiconductor wafer.

3. The wafer of claim 1, further comprising:

at least four integrated circuit devices formed on the first surface of the semiconductor wafer; and

additional pluralities of wire leads, each additional plurality of wire leads being coupled between pairs of the integrated circuit devices.

4. The wafer of claim 3, wherein the covering of encapsulating material substantially covers all pairs of the integrated circuit devices having wire leads coupled thereto.

5. The processed semiconductor wafer of claim 1, wherein the first plurality of contact pads are located proximate a first edge of the first integrated circuit device, said first edge being proximate the second integrated circuit device, and wherein the second plurality of contacts pads are located proximate a second edge of the second integrated circuit device, said second edge being proximate the first integrated circuit device.