Offset control circuit and offset control method

• US 6,291,962 B1
• Filed: 02/16/2000
• Issued: 09/18/2001
• Est. Priority Date: 02/17/1999
• Status: Expired due to Term

• Current Assignee: PHC Holdings Corporation
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ogura, Yoichi, Marukawa, Shoji
• Primary Examiner(s): Masih, Karen
• Application Number:
  US09/504,868
• Time in Patent Office: 580 Days
• Field of Search: 318/609, 318/568.22, 318/635, 318/636, 375/4, 360/51, 360/31
• US Class Current: 318/609
• CPC Class Codes: G11B 11/10515 Reproducing compensating pit shift G11B11/1053
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 2005/0016 of magnetoresistive transducers
• CPC Class Codes: G11B 5/02 Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
• CPC Class Codes: G11B 5/035 Equalising
• CPC Class Codes: G11B 7/005 Reproducing G11B7/0065 takes precedence

Abstract

When a playback signal of recorded data which is a DC free code has non-linearity, the playback signal is equalized by a waveform equalization unit, and sampled by an analog-to-digital converter. The sample data is binarized, and an offset amount is detected by utilizing the feature of the DC free code, and then the reference level of the analog-to-digital converter is controlled so that the output of a first integrator becomes 0. Thereafter, the output of a level shift circuit is input to a second integrator, and the level shift amount is controlled so that the output becomes 0. The converged value is retained. After this learning, by using the retained level shift amount, the reference level is controlled so that the output of the second integrator becomes 0, thereby performing speedy and accurate DC offset control.

Claims

1. An offset control circuit for controlling a DC level of a playback signal when recorded digital data is a DC free code having no DC components and the playback signal has non-linearity, said offset control circuit comprising:

a waveform equalization means for equalizing a predetermined frequency band of the playback signal;

an analog-to-digital converter for sampling the signal equalized by said waveform equalization means to multiple-bit digital data in accordance with a playback clock which is used for reading the signal as digital data;

a binarization means for binarizing the sampled signal;

a converter for outputting opposite-pole values of the same absolute value on the basis of the binarized signal;

a first integrator for integrating the output from said converter;

a level shift circuit for entirely shifting the signal level sampled by said analog-to-digital converter;

a second integrator for integrating the output signal from said level shift circuit;

a shift amount adjustment means for adjusting the shift amount of the said level shift circuit on the basis of the output signal from said second integrator;

a switching means for selecting one of the output signal from said first integrator and the output signal from said second integrator, and outputting the selected signal;

a reference level control circuit for controlling a reference level of said analog-to-digital converter on the basis of the output signal from said switching means; and

a mode controller for switching an operation mode between a training mode and a normal operation mode;

wherein, in the training mode, the reference level is controlled so that the output from said first integrator becomes zero and, after the output from said first integrator converges to zero, in the state where the reference level is held, said shift amount adjustment means is controlled so that the output signal from said second integrator becomes zero, and a convergent value of the shift amount when the output signal from said second integrator is converted to zero is retained in said shift amount adjusting means; and

wherein, in the normal operation mode, the reference level is controlled so that the output signal from said second integrator becomes zero by using the value of the shift amount retained in said shift amount adjustment means, thereby controlling the DC level at high speed.

2. An offset control circuit as claimed in claim 1, further comprising a level fluctuation detector for detecting a time-wise fluctuation of the DC level of the playback signal;

wherein, when said level fluctuation detector decides that the fluctuation is small, the reference level is controlled on the basis of the output signal from said first integrator; and

wherein, when said level fluctuation detector decides that the fluctuation is large, the reference level is controlled on the basis of the output signal from said second integrator.

3. An offset control circuit as claimed in claim 1, wherein said reference level control circuit comprises an adaptive control means which receives the output signals from said first and second integrators, and adjusts amplification factors for the respective signals;

and

wherein the reference level is controlled on the basis of the output from said adaptive control means, thereby adaptively controlling the DC level against non-linear distortions having different characteristics according to the locations.

4. An offset control circuit as claimed in claim 2, wherein said level fluctuation detector comprises:

first and second absolute value converters for receiving the output signals from said first and second integrators, respectively, and for converting the output signals to obtain absolute values;

first and second balancing means for balancing the absolute values outputted from said first and second absolute value converters, respectively;

a counter for counting predetermined periods;

first and second holding means for holding the outputs from said first and second balancing means, respectively, for each predetermined period counted by said counter; and

a fluctuation decision means for detecting fluctuations from the outputs of said first and second holding means and outputting a switching signal.

5. An offset control circuit as claimed in claim 1, wherein said reference level control circuit comprises:

first and second amplifiers for receiving the output signals from said first and second integrators, respectively, and for adjusting the amplification factors of the respective output signals;

a loop filter for receiving the output signal from said first amplifier; and

an adder for receiving the output signal from said second amplifier and for adding the output signal from said second amplifier and the output signal from said loop filter.

6. An offset control circuit as claimed in claim 1, further comprising a level fluctuation detector operable to detect a time-wise fluctuation of the DC level of the playback signal;

wherein, when said level fluctuation detector decides that the fluctuation is small, the reference level is controlled on the basis of the output signal from said first integrator; and

wherein, when said level fluctuation detector decides that the fluctuation is large, the reference level is controlled on the basis of the output signal from said second integrator.

7. An offset control circuit as claimed in claim 1, wherein said reference level control circuit comprises an adaptive control device which is operable to receive the output signals from said first and second integrators, and adjust amplification factors for the respective signals;

and

wherein the reference level is controlled on the basis of the output from said adaptive control device, thereby adaptively controlling the DC level against non-linear distortions having different characteristics according to the locations.

8. An offset control circuit as claimed in claim 6, wherein said level fluctuation detector comprises:

first and second absolute value converters operable to receive the output signals from said first and second integrators, respectively, and operable to convert the output signals to obtain absolute values;

first and second balancing devices operable to balance the absolute values outputted from said first and second absolute value converters, respectively;

a counter operable to count predetermined periods;

first and second holding devices operable to hold the outputs from said first and second balancing devices, respectively, for each predetermined period counted by said counter; and

a fluctuation decision device operable to detect fluctuations from the outputs of said first and second holding devices and outputting a switching signal.

9. An offset control circuit for controlling a DC level of a playback signal when recorded digital data is a DC free code having no DC components and the playback signal has non-linearity, said offset circuit comprising:

a waveform equalization device operable to equalize a predetermined frequency band of the playback signal;

an analog-to-digital converter operable to sample the signal equalized by said waveform equalization device to multiple-bit digital data in accordance with a playback clock which is used for reading the signal as digital data;

a binarization device operable to binarize the sampled signal;

a converter operable to output opposite-pole values of the same absolute value on the basis of the binarized signal;

a first integrator operable to integrate the output from said converter;

a level shift circuit operable to entirely shift the signal level sampled by said analog-to-digital converter;

a second integrator operable to integrate the output signal from said level shift circuit;

a shift amount adjustment device operable to adjust the shift amount of said level shift circuit on the basis of the output signal from said second integrator;

a switching device operable to select one of the output signal from said first integrator and the output signal from said second integrator, and output the selected signal;

a reference level control circuit operable to control a reference level of said analog-to-digital converter on the basis of the output signal from said switching device; and

a mode controller operable to switch an operation mode between a training mode and a normal operation mode;

wherein, in the training mode, the reference level is controlled so that the output from said first integrator becomes zero and, after the output from said first integrator converges to zero, in the state where the reference level is held, said shift amount adjustment device is controlled so that the output signal from said second integrator becomes zero, and a convergent value of the shift amount when the output signal from said second integrator is converted to zero is retained in said shift amount adjusting device; and

wherein in the normal operation mode, the reference level is controlled so that the output signal from said second integrator becomes zero by using the value of the shift amount retained in said shift amount adjustment device, thereby controlling the DC level at high speed.

10. An offset control circuit as claimed in claim 9, wherein said reference level control circuit comprises:

first and second amplifiers operable to receive the output signals from said first and second integrators, respectively, and operable to adjust the amplification factors of the respective output signals;

a loop filter operable to receive the output signal from said first amplifier; and

an adder operable to receive the output signal from said second amplifier and operable to add the output signal from said second amplifier and the output signal from said loop filter.

11. An offset control method employed in an offset control apparatus for controlling the DC level of a playback signal when recorded digital data is a DC free code having no DC components and the playback signal has non-linearity, wherein the offset control apparatus comprises a waveform equalization device, an analog-to-digital converter, a binarization device, a converter, first and second integrators, a level shift circuit, a shift amount adjustment device, a switching device, a reference level control circuit, and a mode controller, said offset control method comprising:

equalizing, using the waveform equalizing device, a predetermined frequency band of the playback signal;

sampling, using the analog-to-digital converter, the signal equalized by the waveform equalizing device to multiple-bit digital data in accordance with a playback clock which is used for reading the signal as digital data;

binarizing the sampled signal;

outputting, using the converter, opposite-pole values of the same absolute value on the basis of the binarized signal;

integrating, using the first integrator, the output from the converter;

entirely shifting, using the level shift circuit, the signal level sampled by the analog-to-digital converter;

integrating, using the second integrator, the output signal from the level shift circuit;

adjusting, using the shift amount adjustment device, the shift amount of the level shift circuit on the basis of the output signal from the second integrator;

selecting, using the switching device, one of the output signal form the first integrator and the output signal from the second integrator, and outputting the selected signal;

controlling, using the reference level control circuit, a reference level of the analog-to-digital converter on the basis of the output signal from the switching device; and

switching, using the mode controller, an operation mode between a training mode and a normal operation mode;

wherein, in the training mode, the reference level is controlled so that the output from the first integrator becomes zero and, after the output from the first integrator converges to zero, in the state where the reference level is held, the shift amount adjustment device is controlled so that the output signal from the second integrator becomes zero and a convergent value of the shift amount, when the output signal from the second integrator is converted to zero, is retained in the shift amount adjusting device; and

wherein, in the normal operation mode, the reference level is controlled so that the output signal from the second integrator becomes zero, by using the value of the shift amount retained in the shift amount adjustment device, thereby controlling the DC level at high speed.

12. An offset control method as claimed in claim 11, wherein the offset control apparatus further comprises a level fluctuation detector for detecting a time-wise fluctuation of the DC level of the playback signal, said offset control method further comprising:

controlling the reference level on the basis of the output signal from the first integrator when the level fluctuation detector decides that the fluctuation is small; and

controlling the reference level on the basis of the output signal from the second integrator when the level fluctuation detector decides that he fluctuation is large.

13. An offset control method as claimed in claim 11, wherein the reference level control circuit comprises an adaptive control device which receives the output signals from the first and second integrators, and adjusts amplification factors for the respective signals, said offset control method further comprising:

controlling the reference level on the basis of the output from the adaptive control device, thereby adaptively controlling the DC level against non-linear distortions having different characteristics according to the locations.