Method for preventing condensation on handler board during semiconductor device testing

• US 6,292,006 B1
• Filed: 08/25/2000
• Issued: 09/18/2001
• Est. Priority Date: 10/10/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Fredrickson, Toby Alan
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US09/648,712
• Time in Patent Office: 389 Days
• Field of Search: 324/760, 324/765, 324/73.1, 324/158.1, 324/755, 324/761, 165/80.4, 165/104.33, 438/14, 438/17, 438/18, 257/48
• US Class Current: 324/750.03
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing

Abstract

A semiconductor device tester and handler interface includes tester and handler boards with a coplanarity plate between them. The handler board includes a central area adapted to mount semiconductor devices to be tested by a tester. The tester board has tester contacts located to interface with a tester. During cold testing, to avoid condensation on the side of the handler board away from the devices being tested, dry gas is applied to the region formed by the coplanarity plate. During hot testing, flowing dry gas prevents the hot handler board from excessively heating the tester board and associated tester.

Claims

1. A method for testing semiconductor devices comprising the steps of:

assembling a tester mother board having a plurality of spring biased pins a handler board having a top side and a bottom side, and a coplanarity plate between the bottom side of the handler board and the tester mother board such that the spring-biased pins extending from the mother board are compressed against contact pads formed on the handler board, the coplanarity plate forming a tight joint to both the mother board and the bottom side of the handler board, forming a central hollow region, and having at least two openings by which gas can be introduced to the hollow region and be discharged,

attaching to a test site located on the top side of the handler board an integrated circuit device to be tested, wherein the handler board includes metallization lines connecting from the contact pads to the test site;

cooling the integrated circuit device to a temperature at which the integrated circuit device is to be tested; and

applying a dry gas to one of the openings of the coplanarity plate, thereby introducing the dry gas to the hollow region.

2. A method for testing semiconductor devices as in claim 1 wherein the flow of dry gas is sufficient to maintain dry gas in the hollow region formed by the coplanarity plate.

4. The method according to claim 1, further comprising transmitting test signals to the integrated circuit device to be tested via the spring-biased pins provided on the mother board.

3. A method for testing semiconductor devices comprising the steps of:

assembling a tester mother board having a plurality of spring biased pins, a handler board having a top side and a bottom side, and a coplanarity plate between the bottom side of the handler board and the tester mother board such that the spring-biased pins extending from the mother board are compressed against contact pads formed on the handler board, the coplanarity plate forming a tight joint to both the mother board and the bottom side of the handler board, forming a central hollow region, and having at least two openings by which gas can be introduced to the hollow region and be discharged,

attaching to a test site located on the top side of the handler board an integrated circuit device to be tested, wherein the handler board includes metallization lines connecting from the contact pads to the test site;

heating the integrated circuit device to a temperature at which the integrated circuit device is to be tested; and

applying a dry gas to one of the openings of the coplanarity plate, thereby introducing the dry gas to the hollow region.

5. The method according to claim 3, further comprising transmitting test signals to the integrated circuit device to be tested via the spring-biased pins provided on the mother board.