FPGA structure having main, column and sector reset lines

• US 6,292,021 B1
• Filed: 08/29/2000
• Issued: 09/18/2001
• Est. Priority Date: 05/20/1996
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Furtek, Frederick C., Mason, Martin T., Luking, Robert B.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/650,979
• Time in Patent Office: 385 Days
• Field of Search: 326/37-41, 326/93
• US Class Current: 326/41
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A field programmable gate array with a matrix of rows and columns of programmable logic cells interconnectable to each other by a network of local and express bus lines and to I/O pads at the perimeter of the logic cell matrix and bus network, is characterized by having a set of reset lines which include main reset lines, column reset lines, and sector reset lines. Each of the main reset lines receives a different reset signal. Each of the column reset lines is associated with a particular column of logic cells of the matrix. Each column reset line is selectively connectable to any one of the main reset lines to receive a selected reset signal. Each of the sector reset lines is connected to a subset of the logic cells in a column. The column reset lines are selective connectable to the logic cells in this respective associated columns by means of the sector reset lines that are connectable to the column reset lines.

Claims

1. A field programmable gate array (FPGA), comprising:

a matrix of rows and columns of programmable logic cells interconnectable to each other and to input and output terminals of the circuit, each logic cell including at least one register element therein with set/reset capability responsive to a set/reset control signal, and

a set of control lines including one global set/reset line receiving said set/reset control signal, a plurality of column set/reset lines connected to said global set/reset line and each associated with a particular column of logic cells, and for each column set/reset line a plurality of sector set/reset lines connectable to that column set/reset line, each sector set/reset line connected to and providing said set/reset control signal to a subset of the logic cells in the associated column of logic cells.

2. The FPGA of claim 1 further comprising a means for selectively inverting said set/reset control signal provided to said subset of a column of logic cells, said means for selectively inverting being located along each sector set/reset line.

3. The FPGA of claim 1 wherein each logic cell has means for selectively designating said set/reset control signal as either a set signal or as a reset signal.