Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit

• US 6,292,116 B1
• Filed: 05/16/2000
• Issued: 09/18/2001
• Est. Priority Date: 05/17/1999
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Sung, Chiakang, Huang, Joseph, Wang, Xiaobao, Wang, Bonnie I., Nguyen, Khai, Kim, In Whan, Yeung, Wayne
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US09/571,766
• Time in Patent Office: 490 Days
• Field of Search: 341/100, 341/101, 375/376
• US Class Current: 341/100
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

Techniques and circuitry are provided to handle high frequency input data. The techniques and circuitry take a high-frequency serial input data stream and covert it into parallel form for handling within the integrated circuit. The circuitry ensures the high frequency data is strobed properly by accounting for skew between the high frequency data input and clock input. In an implementation, multiple clock strobes are generated having the same frequency but different phase. A predetermined series of bits is input to the high frequency input into the circuitry for training. One of the multiple clock strobes is selected based on which one correctly determines the bits in the predetermined input data stream. This clock strobe is selected to strobe the high frequency data input for the integrated circuit. In an embodiment, the high frequency data input is an LVDS input of a programmable logic integrated circuit.

Claims

1. A programmable logic integrated circuit comprising:

a first register coupled to a first input and a first clock signal;

a second register coupled to the first input and a second clock signal;

a multiplexer coupled to outputs of the first and second registers; and

a third register coupled to an output of the multiplexer and a third clock signal, wherein

the first and second clock signals are at a first frequency and have different phases,

the third clock signal is at a second frequency, slower than the first frequency, and a data rate of data appearing at the first input is at about the first frequency.

2. The programmable logic integrated circuit of claim 1 wherein the first frequency is at least twice the second frequency.

3. The programmable logic integrated circuit of claim 1 wherein the first and second clock signals are generated using an on-chip phase locked loop circuit.

4. The programmable logic integrated circuit of claim 1 wherein the first register is part of a first shift register and the second register is part of a second shift register.

5. The programmable logic integrated circuit of claim 1 wherein a selection input of the multiplexer is coupled to a selection register to selectively couple the first or second register to the third register.

6. The programmable logic integrated circuit of claim 5 further comprising:

selection control logic circuitry, coupled to the first and second register and generating an output coupled to the selection register.

7. The programmable logic integrated circuit of claim 1 wherein the first clock signal is programmably selectable to be M times faster than the third clock signal, where M is at least 2.

8. The programmable logic integrated circuit of claim 1 further comprising:

a fourth register coupled to the first input, a fourth clock signal, and the multiplexer; and

a fifth register coupled to the first input, a fifth clock signal, and the multiplexer, wherein the fourth and fifth clock signals are at the first frequency, and the first, second, fourth, and fifth clock signals each have different phases.

9. An integrated circuit comprising:

a high frequency differential data input;

a clock input, wherein a data rate at the data input is at least M times a frequency of a clock signal provided at the clock input, wherein M is an integer 2 or greater;

a differential input buffer coupled to the high frequency data input outputting a single-ended data input;

a clock generator circuit coupled to the clock input and generating a first fast clock signal that is at least M times the clock input;

a first shift register and second shift register coupled to receive serial data from the single-ended data input, wherein the first and second shift registers are clocked using two clock signals having a frequency of the first fast clock signal, but different phases;

a plurality of multiplexers, one for each bit of the first and second shift registers, wherein each multiplexer is coupled to one bit in the first shift register and one bit in the second shift register; and

a third register coupled to the multiplexers.

10. The integrated circuit of claim 9 wherein the first shift register, second shift register, and third register each have eight bits.

11. The integrated circuit of claim 9 wherein the third register is loaded using a load signal at a frequency of the clock input.

12. The integrated circuit of claim 9 wherein the third register is loaded in parallel with the data from the first or second shift register, selected using the multiplexers.

13. The integrated circuit of claim 9 wherein the data from the third register is used to drive programmable interconnect lines of the integrated circuit.

14. A method of operating a programmable logic integrated circuit comprising:

inputting a predetermined stream of bits at a high frequency input;

inputting a clock signal at a clock input;

from the clock signal, generating a first and a second fast clock signal, each having the same frequency but different phase, and the predetermined stream has a frequency of about the first fast clock signal;

loading the predetermined stream in a first shift register using the first fast clock signal;

loading the predetermined stream in a second shift register using the second fast clock signal; and

selectively passing data from the first or second shift register to a third register.

15. The method of claim 14 wherein the first and second fast clock signals are generated using a phase locked loop circuit.

16. The method of claim 14 further comprising:

converting from a differential input at the high frequency input to a single-ended input.

17. The method of claim 14 further comprising:

programmably selecting a frequency of the first fast clock signal to be M times faster than the clock signal, wherein M is 2 or greater.

18. The method of claim 14 further comprising:

loading the predetermined stream in a fourth shift register using a falling edge of the first fast clock signal; and

loading the predetermined stream in a fifth shift register using a falling edge of the second fast clock signal.

19. The method of claim 14 wherein the second fast clock signal is generated by delaying the first fast clock signal.

20. The method of claim 19 further comprising:

loading the predetermined stream in a fourth shift register using a third fast clock signal, generated by delaying the second fast clock signal; and

loading the predetermined stream in a fifth shift register using a fourth fast clock signal, generated by delaying the third fast clock signal.