Liquid crystal display module driving circuit

• US 6,292,182 B1
• Filed: 06/25/1998
• Issued: 09/18/2001
• Est. Priority Date: 06/25/1997
• Status: Expired due to Term

• Current Assignee: BOE HYDIS Technology Company Limited (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Lee, Hyun Kwan, Park, Jin San, Hwang, Soo Woong
• Primary Examiner(s): Shalwala, Bipin
• Assistant Examiner(s): Frenel, Vanel
• Application Number:
  US09/104,719
• Time in Patent Office: 1,181 Days
• Field of Search: 345/95, 345/98, 345/99, 345/100, 345/211, 345/212, 345/213, 340/825.31
• US Class Current: 345/211
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers

Abstract

A circuit for driving a LCM, comprising: a power supply portion for receiving an external voltage of 12V to generate internal voltages of 3.3V and 5V; a clock generation portion for generating a clock signal of desired frequency; a driving signal generation portion for receiving the clock signal from the clock generation portion to generate driving signals of a data enable signal, a horizontal synchronous signal, a vertical synchronous signal, and an enable signal; a signal selection portion for selecting the desired signals of the driving signals from the driving signal generation portion and outputting the selected driving signals and the clock signal from the clock generation portion; a state detection portion for receiving the vertical synchronous signal and the external voltage of 5V to detect a normal operation state of the LCM; a power selection portion for selecting one of an external voltage of 5V and the external voltage of 12V in accordance with application of the internal voltage of 5V; and an output portion for outputting the selected driving signals and clock signal from the signal selection portion, the selected power voltage from the power selection portion and a state detection signal from the state detection portion.

Claims

1. A circuit for driving an LCM, comprising:

a power supply portion for receiving an external voltage of 12V to generate internal voltages of 3.3V and 5V;

a clock generation portion for generating a clock signal of desired frequency;

a driving signal generation portion for receiving the clock signal from the clock generation portion to generate driving signals, the driving signals including a data enable signal, a horizontal synchronous signal, a vertical synchronous signal, and an enable signal;

a signal selection portion for selecting the desired signals of the driving signals from the driving signal generation portion and outputting the selected driving signals and the clock signal from the clock generation portion;

a state detection portion for receiving the vertical synchronous signal and an external voltage of 5V to detect a normal operation state of the LCM so as to produce a state detection signal;

a power selection portion for selecting a power voltage from one of the external voltage of 5V and the external voltage of 12V in accordance with application of the internal voltage of 5V; and

an output portion for outputting the selected driving signals and the clock signal from the signal selection portion, the selected power voltage from the power selection portion and the state detection signal from the state detection portion,

wherein the driving signal generation portion includes;

a counting portion for counting the clock signal from the clock generation portion;

a data enable signal generation portion for receiving outputs of the counting portion to generate the data enable signal;

a vertical synchronous signal generation portion for receiving the data enable signal from the data enable signal generation portion to generate the vertical synchronous signal;

a horizontal synchronous signal generation portion for receiving the output signals from the counting portion to generate the horizonital synchronous signal;

an enable signal generation portion for receiving the data enable signal from the data enable signal generation portion and the vertical synchronous signal from the vertical synchronous signal generation portion; and

a power stabilizing portion for stabilizing the internal voltage of 5V which is provided to the data enable signal generation portion, the horizontal synchronous signal generation portion and the vertical synchronous signal generation portion.

2. The LCM driving circuit as claimed in claim 1, further comprising a circuit protection portion for protecting the driving circuit by selecting an external voltage when one of the external voltages and one of the internal voltages are simultaneously applied to the driving circuit.

3. The LCM driving circuit as claimed in claim 2, wherein the circuit protection portion includes:

a first protection portion for selecting the external voltage of 12V, when the external voltage of 12V and the internal voltage of 12V are simultaneously applied; and

a second protection portion for selecting the external voltage of 5V, when the external voltage of 5V and the internal 5V are simultaneously applied.

4. The LCM driving circuit as claimed in claim 1, wherein the power supply portion includes:

a first generation portion for receiving the external voltage of 12V to generate the internal voltage of 5V; and

a second generation portion for receiving the external voltage of 12V to generate the internal voltage of 3.3V.

5. The LCM driving circuit as claimed in claim 1, wherein the signal selection portion includes:

a transfer portion for transferring the driving signals from the driving signal generation portion and the clock signal from the clock generation portion to the output portion; and

a selection portion for selecting the desired signals of the driving signals from the driving signal generation portion according to operation mode of the LCM to be transferred to the output portion.

6. The LCM driving circuit as claimed in claim 1, wherein the power selection portion includes:

a first selection portion for providing the external voltage of 5V to the output portion in accordance with application of the internal voltage of 5V from the power supply portion; and

a second selection portion for providing the external voltage of 12V to the output portion in accordance with application of the internal voltage of 5V.

7. The LCM driving circuit as claimed in claim 6, wherein the first selection portion includes:

an inverter for detecting application of the internal voltage of 5V from the power supply portion;

a first transistor for providing the external voltage of 5V to the output portion according to a detection result of the inverter; and

first and second resistors for supplying the external voltage of 5V to a base and collector of the first transistor, respectively.

8. The LCM driving circuit as claimed in claim 7, wherein the second selection portion includes:

third and fourth resistors for dividing the internal voltage of 5V from the power supply portion; and

a second transistor for providing the external voltage of 12V to the output portion in accordance with the divided voltage.

9. The LCM driving circuit as claimed in claim 1, wherein the state detection portion includes:

an AND gate for receiving the vertical synchronous signal from the driving signal generation portion and the internal voltage of 5V from the power supply portion to detect the normal operation state of the LCM; and

a transistor for providing a voltage of 0V in normal operation or the external voltage of 12V in abnormal operation to the output portion in accordance with an output of the AND gate.

10. The LCM driving circuit as claimed in claim 1, wherein the clock generation portion generates the clock signal having one of 25.175 MHz, 40 MHz, or 65 MHz.

11. A circuit for driving an LCM, comprising:

a power supply portion for receiving an external voltage of 12V to generate internal voltages of 3.3V and 5V;

a clock generation portion for generating a clock signal CLK of 65 MHz and an inverted clock signal;

a driving signal generation portion for receiving the clock signal from the clock generation portion to generate driving signals, the driving signals including a data enable signal of 800 CLK a vertical synchronous signal of 600 H, and an enable signal;

a signal selection portion for selecting the desired signals of the driving signals from the driving signal generation portion and outputting the selected driving signals and the clock signal from the clock generation portion;

a state detection portion for receiving the vertical synchronous signal and an external voltage of 5V to detect a normal operation state of the LCM so as to produce a state detection signal;

a power selection portion for selecting a power voltage from one of the external voltage of 5V and the external voltage of 12V in accordance with application of the internal voltage of 5V;

a pattern selection portion for selecting one of a black pattern or a black and white pattern as a pattern being displayed on an LCD panel; and

an output portion for outputting the selected driving signals and the clock signal from the signal selection portion, the selected power voltage from the power selection portion, the clock signal from the clock generation portion and the state detection signal from the state detection portion,

wherein the driving signal generation portion includes;

a counting portion for counting the clock signal from the clock generation portion;

a data enable signal generation portion for receiving outputs of the counting portion to generate the data enable signal of 800 CLK;

a vertical synchronous signal generation portion for receiving the data enable signal from the data enable signal generation portion to generate the vertical synchronous signal of 600 H;

an enable signal generation portion for receiving the data enable signal from the data enable signal generation portion and the vertical synchronous signal from the vertical synchronous signal generation portion to generate the enable signal; and

a power stabilizing portion for stabilizing the internal voltage of 5V which is provided to the data enable signal generation portion, and the vertical synchronous signal generation portion.

12. The LCM driving circuit as claimed in claim 11, wherein the counting portion is comprised of a first counter which is triggered at a falling edge of the inverted clock signal from the clock generation portion to count the clock signal and generate first through twelfth output signals.

13. The LCM driving circuit as claimed in claim 12, wherein the data enable signal generation portion includes:

a first NAND gate for receiving the ninth output signal of the first counter;

a second NAND gate for receiving the sixth and eleventh output signals of the first counter;

a first flip flop which receives an output signal of the first NAND gate as an input signal and is triggered at a rising edge of the clock signal from the clock generation portion;

a second flip flop which receives an output signal of the second NAND gate as an input signal, is triggered at a rising edge of the clock signal and provides its inverted output signal to the first counter as a reset signal; and

a third flip flop which receives output signals of the first and second flip flops as a preset signal and a clear signal, respectively, and generates the data enable signal of 800 CLK as an output signal.

14. The LCM driving circuit as claimed in claim 13, wherein the vertical synchronous signal generation portion includes:

a second counter which is triggered at a falling edge of the data enable signal received from the data enable signal generation portion to count the data enable signal and generates first through twelfth output signals;

a third NAND gate for receiving the third through fifth output signals of the second counter;

a first AND gate for receiving the fifth and sixth output signals of the second counter;

a second AND gate for receiving the seventh and tenth output signals of the second counter;

a fourth NAND gate for receiving output signals of the first and second AND gates and the third output signals of the second counter;

an inverter for inverting the data enable signal generated from the data enable signal generation portion;

a fourth flip flop which receives an output signal of the third NAND gate as an input signal and is triggered at a rising edge of an inverted data enable signal received from the inverter;

a fifth flip flop which receives an output signal of the fourth NAND gate as an input signal and is triggered at a rising edge of the inverted data enable signal; and

a sixth flip flop which receives output signals of the fourth and fifth flop flops as a preset signal and a clear signal, respectively, and generates the vertical synchronous signal of 600 H as an output signal.

15. The LCM driving circuit as claimed in claim 14, wherein the enable signal generation portion includes a third AND gate for receiving the data enable signal from the data enable signal generation portion and the vertical synchronous signal from the vertical synchronous signal generation portion.

16. The LCM driving circuit as claimed in claim 11, wherein the signal selection portion includes;

a transfer portion for transferring the data enable signal, the vertical synchronous signal and the enable signal from the driving signal generation portion and the clock signal from the clock generation portion; and

a selection portion for selecting the enable signal and clock signal from the transfer portion to be transferred to the output portion.

17. The LCM driving circuit as claimed in claim 16, wherein the transfer portion includes:

an output buffer for receiving the data enable signal, the vertical synchronous signal and the enable signal from the driving signal generation portion; and

a plurality of buffers for protection for transferring the enable signal and the vertical synchronous signal from the output buffer and the clock signal from the clock generation portion.

18. The LCM driving circuit as claimed in claim 17, wherein the selection portion comprises a switch for selecting the enable signal and clock signal received from the transfer portion.

19. The LCM driving circuit as claimed in claim 11, wherein the pattern selection portion includes:

a jumper switch for selecting the black and white pattern;

a timer for adjusting the period of the black and white pattern selected by the jumper switch; and

a flip flop which receives an output of the timer as an input signal and is triggered at a rising edge of the data enable signal from the data enable signal generation portion to provide the period of the black and white pattern to the output portion.

20. A circuit for driving a liquid crystal display module (LCM), comprising:

a power supply portion for receiving an external voltage of 12V to generate an internal voltage of 5V and an internal voltage of 3.3V;

a clock generation portion for generating a clock signal CLK of 25.175 MHz and an inverted clock signal;

a driving signal generation portion for receiving the clock signal and the inverted clock signal to generate driving signals, the driving signals including a data enable signal of 640 CLK, a vertical synchronous signal of 480 H, a horizontal synchronous signal and an enable signal;

a signal selection portion for selecting the desired signals of the driving signals according to an operation mode of the LCM and providing the selected driving signals and the clock signal from the clock generation portion;

a state detection portion for receiving the vertical synchronous signal and an external voltage of 5V to detect an operation state of the circuit so as to produce a state detection signal;

a power selection portion for selecting a power voltage from the external voltage of 5V or the external voltage of 12V according to the application of the internal voltage of 5V; and

an output portion for outputting the selected driving signals and the clock signal received from the signal selection portion, the power voltage selected from the power selection portion, and the state detection signal received from the state detection portion,

wherein the driving signal generation portion includes;

a counting portion which is triggered at a falling edge of the inverted clock signal from the clock generation portion to count the clock signal;

a data enable signal generation portion for receiving output signals from the counting portion to generate the data enable signal of 640 CLK;

a horizontal synchronous signal generation portion for receiving the output signals from the counting portion to generate the horizontal synchronous signal;

a vertical synchronous signal generation portion for receiving the data enable signal from the data enable signal generation portion to generate the vertical synchronous signal of 480 H;

an enable signal generation portion for receiving the data enable signal and the vertical synchronous signal to generate the enable signal; and

a stabilizing means for stabilizing the internal voltage of 5V which is provided to the data enable signal generation portion, the vertical synchronous signal generation portion and the horizontal synchronous signal generation portion.

21. The LCM driving circuit as claimed in claim 20, wherein the counting portion includes a first counter which is triggered at a falling edge of the inverted clock signal from the clock generation portion and provides first through twelfth output signals.

22. The LCM driving circuit as claimed in claim 21, wherein the data enable signal generation portion includes:

a first NAND gate for receiving the sixth output signal and the eighth output signal received from the first counter;

a second NAND gate for receiving the sixth output signal, the ninth output signal and the tenth output signal received from the first counter;

a first flip flop which receives an output signal of the first NAND gate as an input signal and is triggered at a rising edge of the clock signal from the clock generation portion;

a second flip flop which receives an output signal of the second NAND gate and is triggered at a rising edge of the clock signal from the clock generation portion to generate its inverted output signal to the first counter of the counting portion as a reset signal; and

a third flip flop which receives output signals of the first and second flip flops as a preset signal and a clear signal and generates the data enable signal of 640 CLK as an output signal.

23. The LCM driving circuit as claimed in claim 22, wherein the horizontal synchronous signal generation portion includes:

a third NAND gate for receiving the sixth output signal and the seventh output signal received from the first counter;

a fourth flip flop which receives an output signal of the third NAND gate as an input signal and is triggered at a rising edge of the clock signal from the clock generation portion; and

a fifth flip flop which receives an output signal of the fourth flip flop and the output signal of the second flip flop as a preset signal and a clear signal and generates the horizontal synchronous signal as an output signal.

24. The LCM driving circuit as claimed in claim 23, wherein the vertical synchronous signal generation portion includes:

a second counter which is triggered at a falling edge of the data enable signal from the data enable signal generation portion and provides first through twelfth output signals;

a fourth NAND gate for receiving the third output signal, the fourth output signal and the tenth output signal received from the second counter;

a fifth NAND gate for receiving the third output signal, the fourth output signal and the sixth output signal received from the second counter;

an inverter for inverting the data enable signal received from the data enable signal generation portion;

a sixth flip flop which receives the second output signal of the second counter as an input signal and is triggered at a rising edge of an inverted data enable signal from the inverter;

a seventh flip flop which receives an output signal of the fourth NAND gate and is triggered at a rising edge of the inverted data enable signal from the inverter to generate an inverted output signal as a reset signal of the second counter;

an eighth flip flop which receives output signals of the sixth and seventh flip flops as a preset signal and a clear signal and provides the vertical synchronous signal as an output signal;

a ninth flip flop which receives an output signal of the sixth NAND gate and is triggered at a rising edge of the inverted data enable signal; and

a tenth flip flop which receives an output signal from the ninth flip flop and the output signal of the seventh flip flop as a preset signal and a clear signal.

25. The LCM driving circuit as claimed in claim 24, wherein the enable signal generation portion includes an AND gate which receives the data enable signal from the data enable signal generation portion and an output signal of the tenth flip flop of the vertical synchronous signal generation portion.

26. The LCM driving circuit as claimed in claim 20, wherein the signal selection portion includes:

a selection portion for selecting the desired signals of the data enable synchronous signal, the horizontal synchronous signal, the vertical synchronous signal and the enable signal received from the driving signal generation portion; and

a transfer portion for transferring the selected driving signals from the selection portion and the clock signal received from the clock generation portion.

27. A circuit for driving a liquid crystal display module (LCM), comprising:

a power supply portion for receiving an external voltage of 12V to generate an internal voltage of 5V and an internal voltage of 3.3V;

a clock generation portion for generating a clock signal CLK of 60 MHz and an inverted clock signal;

a driving signal generation portion for receiving the clock signal and the inverted clock signal to generate driving signals, the driving signals including a data enable signal of 1024 CLK a vertical synchronous signal of 768 H, a horizontal synchronous signal, and an enable signal;

a signal selection portion for selecting the desired signals of the driving signals according to an operation mode of the LCM and providing the selected driving signals and the clock signal from the clock generation portion;

a state detection portion for receiving the vertical synchronous signal and an external voltage of 5V to detect an operation state of the LCD driving circuit so as to produce a state detection signal;

a power selection portion for selecting a power voltage from the external voltage of 5V or the external voltage of 12V according to the application of the internal voltage of 5V; and

an output portion for outputting the selected driving signals and the clock signal received from the signal selection portion, the power voltage selected from the power selection portion, and the state detection signal received from the state detection portion,

wherein the driving signal generation portion includes;

a counting portion which is triggered at a falling edge of the inverted clock signal from the clock generation portion to count the clock signal;

a data enable signal generation portion for receiving output signals from the counting portion to generate the data enable signal of 1024 CLK;

a horizontal synchronous signal generation portion for receiving the output signals from the counting portion to generate the horizontal synchronous signal;

a vertical synchronous signal generation portion for receiving the data enable signal from the data enable signal generation portion to generate the vertical synchronous signal of 768 H;

an enable signal generation portion for receiving the data enable signal and the vertical synchronous signal to generate the enable signal; and

a stabilizing means for stabilizing the internal voltage of 5V which is provided to the data enable signal generation portion, the vertical synchronous signal generation portion and the horizontal synchronous signal generation portion.

28. The LCM driving circuit as claimed in claim 27, wherein the counting portion includes a first counter which is triggered at a falling edge of the inverted clock signal from the clock generation portion and provides first through twelfth output signals.

29. The LCM driving circuit as claimed in claim 28, wherein the data enable signal generation portion includes:

a first NAND gate for receiving the sixth output signal and the eighth output signal received from the first counter;

a second NAND gate for receiving the sixth output signal, the eighth output signal and the tenth output signal received from the first counter;

a first flip flop which receives an output signal of the first NAND gate as an input signal and is triggered at a rising edge of the clock signal from the clock generation portion;

a second flip flop which receives an output signal of the second NAND gate and is triggered at a rising edge of the clock signal from the clock generation portion to generate its inverted output signal to the first counter of the counting portion as a reset signal; and

a third flip flop which receives output signals of the first and second flip flops as a preset signal and a clear signal and generates the data enable signal of 640 CLK as an output signal.

30. The LCM driving circuit as claimed in claim 29, wherein the horizontal synchronous signal generation portion includes:

a third NAND gate for receiving the third output signal and the seventh output signal received from the first counter;

a fourth flip flop which receives an output signal of the third NAND gate as an input signal and is triggered at a rising edge of the clock signal from the clock generation portion; and

a fifth flip flop which receives an output signal of the fourth flip flop and the output signal of the second flip flop as a preset signal and a clear signal and generates the horizontal synchronous signal as an output signal.

31. The LCM driving circuit as claimed in claim 30, wherein the vertical synchronous signal generation portion includes:

a second counter which is triggered at a falling edge of the data enable signal from the data enable signal generation portion and provides first through twelfth output signals;

a fourth NAND gate for receiving the second output signal and the third output signal received from the second counter;

a first AND gate for receiving the second and third output signals of the second counter;

a second AND gate for receiving the sixth output signal and the ninth output signal of the second counter;

a fifth NAND gate for receiving output signals of the first and second AND gates;

a sixth NAND gate for receiving the second and third output signals and the sixth output signal of the second counter;

an inverter for inverting the data enable signal received from the data enable signal generation portion;

a sixth flip flop which receives an output signal of the fourth NAND gate as an input signal and is triggered at a rising edge of an inverted data enable signal from the inverter;

a seventh flip flop which receives an output signal of the fifth NAND gate and is triggered at a rising edge of the inverted data enable signal from the inverter;

an eighth flip flop which receives output signals of the sixth and seventh flip flops as a preset signal and a clear signal and generates the vertical synchronous signal as an output signal;

a ninth flip flop which receives an output signal of the sixth NAND gate and is triggered at a rising edge of the inverted data enable signal; and

a tenth flip flop which receives an output signal from the ninth flip flop and the output signal of the seventh flip flop as a preset signal and a clear signal.

32. The LCM driving circuit as claimed in claim 31, wherein the enable signal generation portion includes an AND gate which receives the data enable signal from the data enable signal generation portion and an output signal of the tenth flip flop of the vertical synchronous signal generation portion.

33. The LCM driving circuit as claimed in claim 27, wherein the signal selection portion includes:

a selection portion for selecting the desired signals of the data enable synchronous signal, the horizontal synchronous signal, the vertical synchronous signal and the enable signal received from the driving signal generation portion; and

a transfer portion for transferring the selected driving signals from the selection portion and the clock signal received from the clock generation portion.