Method for programming of a semiconductor memory cell

• US 6,292,394 B1
• Filed: 06/29/2000
• Issued: 09/18/2001
• Est. Priority Date: 06/29/2000
• Status: Expired due to Term

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo, Cohen, Zeev
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/606,205
• Time in Patent Office: 446 Days
• Field of Search: 365/185.19, 365/185.03, 365/185.22, 365/185.14, 365/185.29
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A method for programming an array having a multiplicity of memory cells. The method includes, per cell to be programmed, verifying a programmed or non-programmed state of the cell and flagging those of the cells that verify as non-programmed during one of the verify steps after having previously verified as programmed. A programming pulse having a programming level is applied to the non-programmed cells which are not flagged cells. The steps of verifying, flagging and applying are then repeated until all of the cells verify as programmed at least once. Subsequently, a boost pulse having a boost programming level lower than the programming level is applied to the flagged cells.

Claims

1. A method for programming an array having a multiplicity of memory cells, the method comprising the steps of:

per cell to be programmed, verifying a programmed or non-programmed state of said cell;

flagging those of said cells that verify as non-programmed during one of said verify steps after having previously verified as programmed;

applying a programming pulse having a programming level to said non-programmed cells which are not flagged cells;

repeating said steps of verifying, flagging and applying until all of said cells verify as programmed at least once; and

applying a boost pulse having a boost programming level lower than said programming level to said flagged cells.

2. A method according to claim 1, wherein said step of repeating comprises the step of increasing said programming level of said programming pulse.

3. A method according to claim 2, wherein said step of increasing comprises the step of increasing said programming level by between 0.05 to 0.3 volts.

4. A method according to claim 2, wherein said step of increasing comprises the step of determining said programming level by external means.

5. A method according to claim 2, wherein said step of increasing comprises the step of increasing said programming level by constant voltage steps.

6. A method according to claim 2, wherein said step of increasing comprises the step of increasing said programming level by variable voltage steps.

7. A method according to claim 1, wherein said programming pulses vary in length of time.

8. A method according to claim 1, and wherein said first step of applying comprises the step of applying a programming pulse to a gate, a drain, or a source of said non-programmed cells which are not flagged cells.

9. A method according to claim 1, wherein said step of verifying comprises the step of determining a verifying level by external means.

10. A method according to claim 1, wherein said step of verifying comprises the step of determining a verifying level having a constant voltage level.

11. A method according to claim 1, wherein said step of verifying comprises the step of determining a verifying level having a variable voltage level.

12. A method according to claim 1, wherein said step of verifying comprises the step of verifying whether a threshold voltage of a call is below a determined level.

13. A method for erasing an array having a multiplicity of memory cells, the method comprising the steps of:

per cell to be erased, verifying an erased or non-erased state of said cell;

flagging those of said cells that verify as non-erased during one of said verify steps after having previously verified as erased;

applying an erasing pulse having an erasure level to said non-erased cells which are not flagged cells;

repeating said steps of verifying, flagging and applying until all of said cells have verified as said erased at least once; and

applying a boost pulse having a boost erase level lower than said erased level to said flagged cells.

14. A method according to claim 13, wherein said step of repeating comprises the step of increasing said erasure level of said erasing pulse.

15. A method according to claim 14, wherein said step of increasing comprises the step of increasing said erasure level by between 0.05 to 0.3 volts.

16. A method according to claim 14, wherein said step of increasing comprises the step of determining said erasure level by external means.

17. A method according to claim 14, wherein said step of increasing comprises the step of increasing said erasure level by constant voltage steps.

18. A method according to claim 14, wherein said step of increasing comprises the step of increasing said erasure level by variable voltage steps.

19. A method according to claim 13, wherein said erasure pulses vary in length of time.

20. A method according to claim 13, wherein said first step of applying comprises the step of applying a programming pulse to a gate, a drain, or a source of said non-programmed cells which are not flagged cells.

21. A method according to claim 13, wherein said step of verifying comprises the step of determining a verifying level by external means.

22. A method according to claim 13, wherein said step of verifying comprises the step of determining a verifying level having a constant voltage level.

23. A method according to claim 13, wherein said step of verifying comprises the step of determining a verifying level having a variable voltage level.

24. A method according to claim 13, wherein said step of verifying comprises the step of verifying whether a threshold voltage of a cell is above a determined level.

25. A method for programming an array having a multiplicity of memory cells, the method comprising the steps of:

per cell to be programmed, verifying a coarse programmed or non-programmed state of said cell;

flagging those of said cells that verify as non-programmed during one of said verify steps after having previously verified as programmed;

applying a coarse programming pulse having a coarse programming level to said non-programmed cells which are not flagged cells;

repeating said steps of verifying, flagging and applying until all of said cells verify as programmed at least once;

applying a fine programming pulse to said flagged cells;

verifying a complete programmed state or a complete non-programmed state of said cell; and

repeating the second steps of verifying and applying until all of said cells are very as fully programmed at least once.

26. A method according to claim 25, wherein the first step of verifying comprises verifying a cell threshold voltage to a level that is within α

volts of a desired threshold voltage.

27. A method according to claim 26, wherein α

is in the range of 0.2-0.5 volt.

28. A method according to claim 26, wherein α

is the maximum change in threshold voltage that can be induced in a cell with a coarse programming pulse.

29. A method according to claim 25, wherein said second step of verifying comprises the steps of:

verifying if a threshold voltage of said cell is within α

volts of a desired threshold voltage; and

if said verified level is greater than said α

volts, repeating said first steps of verifying, flagging and applying until all of said cells verify with within α

volts of a desired threshold voltage.

30. A method for an array having a multiplicity of memory cells, the method comprising the steps of:

per cell to be programmed, verifying a programmed or non-programmed state of said cell;

flagging those of said cells that verify as non-programmed during one of said program verify steps after having previously verified as programmed;

applying a programming pulse having a programming level to said non-programmed cells which are not flagged cells;

applying a recovery pulse having a recovery level lower than said programming level to said flagged cells; and

repeating said steps of verifying, flagging, applying and applying until all of said cells verify as said programmed at least once.

31. A method according to claim 30, wherein said recovery level is 0.05V.