Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode

• US 6,292,399 B1
• Filed: 07/03/2000
• Issued: 09/18/2001
• Est. Priority Date: 07/03/2000
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Van Buskirk, Michael A., Chen, Pau-Ling, Le, Binh Q.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/609,897
• Time in Patent Office: 442 Days
• Field of Search: 365/226, 365/185.21, 365/185.2, 365/189.07, 365/189.09
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.

Claims

1. A control circuit for generating an accurate drain voltage for selected memory core cells in a semiconductor memory circuit during a Read mode of operation, said control circuit comprising:

selected gate transistors each having its conductive path being coupled between a power supply voltage and a drain of one of the selected memory core cells;

differential amplifier means responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage which is decreased when the bitline voltage is higher than a target voltage and which is increased when the bitline voltage is lower than the target voltage;

said differential amplifier circuit means including a first input transistor having its gate connected to a stable reference voltage and a second input transistor having its gate coupled to a feedback voltage which is proportional to the bitline voltage, the second input transistor having its collector providing the select gate voltage;

a capacitor divider network formed of a first capacitor and a second capacitor connected in series between the bitline voltage and a ground potential, the junction of said first and second capacitors providing the feedback voltage;

source follower circuit means responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage;

said source follower circuit means being formed of a plurality of transistors whose drains are coupled together and to the power supply potential, gates are connected together and to receive the select gate voltage, and sources are connected together and to provide the bitline voltage; and

the control gates of the select gate transistors being connected to receive said select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.

2. A control circuit for generating an accurate drain voltage as claimed in claim 1, further comprising a first constant current source transistor having its drain connected to the sources of said first and second input transistors, its source connected to the ground potential, and its gate connected to receive a bias voltage.

3. A control circuit for generating an accurate drain voltage as claimed in claim 2, further comprising reference voltage generator means for generating the stable reference voltage.

4. A control circuit for generating an accurate drain voltage as claimed in claim 3, further comprising bias generator means for generating the bias voltage.

5. A control circuit for generating an accurate drain voltage as claimed in claim 4, further comprising a second current source transistor having its drain connected to receive the bitline voltage, its source connected to the ground potential, and its gate connected to receive the bias voltage.

6. A control circuit for generating an accurate drain voltage as claimed in claim 1, wherein the size of the second input transistor is n times larger than the size of the first input transistor so as to create an unbalanced differential amplifier circuit.

7. A control circuit for generating an accurate drain voltage as claimed in claim 1, wherein said power supply voltage is in the range of +2.6 V to +3.6 V.

8. A control circuit for generating an accurate drain voltage as claimed in claim 7, wherein the reference voltage is approximately +1.3 V.

9. A control circuit for generating an accurate drain voltage as claimed in claim 8, wherein the target voltage is approximately +1.5 V.

10. A control circuit for generating an accurate drain voltage as claimed in claim 1, wherein the feedback voltage is substantially equal to the reference voltage when the bitline voltage is at the target voltage.

11. A control circuit for generating an accurate drain voltage as claimed in claim 1, wherein the drains of said first and second input transistors are coupled to a boosted voltage.

12. A control circuit for generating an accurate drain voltage as claimed in claim 11, wherein said boosted voltage is in the range of +4.4 V to +6.3 V.