Enhancements in testing devices on burn-in boards

• US 6,292,415 B1
• Filed: 09/28/1999
• Issued: 09/18/2001
• Est. Priority Date: 09/28/1999
• Status: Expired due to Term

• Current Assignee: AEHR Test Systems
• Original Assignee: AEHR Test Systems
• Inventors: Brehm, Jeffrey A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/407,659
• Time in Patent Office: 721 Days
• Field of Search: 365/201, 365/194, 365/191, 365/243, 365/198
• US Class Current: 365/201
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

A system for testing semiconductor devices on device test boards has a single tester channel connected to multiple DUTs in a loop. Outputs from DUTs are received at a comparator and latch after a period of Round Trip Delay (RTD). The comparator is connected in a parallel configuration with the return path of the loop, where the point of connection is in greater proximity to DUT output pins than the test channel and is a path different from the tester I/O driver path, thus preventing input signals from test drivers from interfering with output signals from DUTs that will serve as inputs to test circuitry. The time it takes a new input cycle state to reach the output comparator is long after the output from a prior cycle has been tested. A diode clamp and resistor are connected in a series with the comparator at the input stage near the comparator in order to reduce ringing at the input of the comparator, which limits tester speed. Bus-switches composed of Field Effect Transistors (FET) electrically switch the input/output (I/O) of DUTs being tested to either exclusively drive or receive trace lines, respectively, reducing DUT pin loading and thus increasing achievable testing speed. The improved testing system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

Claims

1. A semiconductor device parallel test and burn-in system, which comprises:

a pattern generator for generating a plurality of test signals for the semiconductor devices;

an interface for coupling a plurality of semiconductor devices in parallel to said pattern generator; and

a plurality of data output comparators coupled to said interface so that one of said plurality of data output comparators can be coupled to each of said plurality of semiconductor devices;

where said interface and said data output comparators are coupled to substantially eliminate round trip delay.

2. The semiconductor device burn-in system of claim 1 in which said interface and said plurality of data output comparators are coupled to substantially eliminate round trip delay by providing one of said data output comparators having an input adjacent to a separate test output connection of each of said plurality of semiconductor devices under test.

3. A semiconductor device parallel test and burn-in system, which comprises:

a pattern generator for generating a plurality of test signals for the semiconductor devices;

an interface for coupling a plurality of semiconductor devices in parallel to said pattern generator; and

a plurality of data output comparators coupled to said interface so that one of said plurality of data output comparators can be coupled to each of said plurality of semiconductor devices;

where said interface and said data output comparators are coupled to substantially eliminate round trip delay by providing one of said data output comparators having an input adjacent to a separate test output connection of each of said plurality of semiconductor devices under test;

said system further comprising a diode clamp connected between the test output connection of each of said plurality of semiconductor devices under test and said data output comparator.

4. A semiconductor device parallel test and burn-in system, which comprises:

a pattern generator for generating a plurality of test signals for the semiconductor devices;

an interface for coupling a plurality of semiconductor devices in parallel to said pattern generator; and

a plurality of data output comparators coupled to said interface so that one of said plurality of data output comparators can be coupled to each of said plurality of semiconductor devices;

where said interface and said data output comparators are coupled to substantially eliminate round trip delay by providing one of said data output comparators having an input adjacent to a separate test output connection of each of said plurality of semiconductor devices under test;

said system further comprising a first output bus switch connected between the test output connection of each of said plurality of semiconductor devices under test and said data output comparator.

5. The semiconductor device parallel test and burn-in system of claim 4 additionally comprising a tester input/output driver capable of being driven in an input mode and an output mode coupled between said pattern generator and the test output connection of each of said plurality of semiconductor devices under test through a second output bus switch.

6. The semiconductor device parallel test and burn-in system of claim 5 in which said first output bus switch comprises a first field effect transistor.

7. The semiconductor device parallel test and burn-in system of claim 6 in which said second output bus switch comprises a second field effect transistor.

8. The semiconductor device parallel test and burn-in system of claim 7 in which said first and second field effect transistors are provided in said interface and said device parallel test and burn-in system additionally includes at least one semiconductor device test board connected to said interface and including the plurality of semiconductor devices under test.

9. The semiconductor device parallel test and burn-in system of claim 7 in which said device parallel test and burn-in system additionally includes at least one semiconductor device test board connected to said interface and including the plurality of semiconductor devices under test, said first and second field effect transistors being provided in said semiconductor device test board.

10. The semiconductor device parallel test and burn-in system of claim 9 in which said first field effect transistor is provided in a multiplexer circuit between the plurality of semiconductor devices under test and said data output comparator.

11. A semiconductor device parallel test and burn-in system, which comprises:

a pattern generator for generating a plurality of test signals for the semiconductor devices;

an interface for coupling a plurality of semiconductor devices in parallel to said pattern generator; and

a plurality of data output comparators coupled to said interface so that one of said plurality of data output comparators can be coupled to each of said plurality of semiconductor devices;

where said interface and said data output comparators are coupled to substantially eliminate round trip delay; and

where one of said plurality of data output comparators is coupled to each of the plurality of semiconductor devices through a multiplexer.

12. A method for burn-in testing of a plurality of semiconductor devices, which comprises:

providing a plurality of burn-in test signals to an input of each of the plurality of semiconductor devices;

coupling a data output comparator to an output of each of the plurality of semiconductor devices in a manner to substantially eliminate round trip delay; and

providing data output signals from each of the plurality of semiconductor devices to the data output comparator.

13. The method for burn-in testing of claim 12 in which the data output comparator is coupled to substantially eliminate round trip delay by providing the data output comparator having an input adjacent to a separate test output connection of each of said plurality of semiconductor devices under test.

14. The method for burn-in testing of claim 13 additionally comprising:

connecting a diode clamp between the test output connection of each of the plurality of semiconductor devices under test and the data output comparator.

15. The method for burn-in testing of claim 13 additionally comprising:

connecting a first output bus switch between the test output connection of each of the plurality of semiconductor devices under test and the data output comparator.

16. The method for burn-in testing of claim 15 additionally comprising:

connecting a tester input/output driver capable of being driven in an input mode and an output mode between said pattern generator and the test output connection of each of said plurality of semiconductor devices under test through a second output bus switch.

17. The method for burn-in testing of claim 16 in which the first output bus switch comprises a first field effect transistor.

18. The method for burn-in testing of claim 17 in which the second output bus switch comprises a second field effect transistor.

19. The method for burn-in testing of claim 18 in which the first field effect transistor is provided in a multiplexer circuit between the plurality of semiconductor devices under test and the data output comparator.

20. The method for burn-in testing of claim 12 in which the one of said plurality of data output comparators is coupled to each of the plurality of semiconductor devices through a multiplexer.