Reduction of time error in GPS localization without a highly accurate clock

• US 6,292,748 B1
• Filed: 07/14/2000
• Issued: 09/18/2001
• Est. Priority Date: 07/14/2000
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Harrison, Daniel David
• Primary Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US09/617,022
• Time in Patent Office: 431 Days
• Field of Search: 701/213, 701/214, 701/215, 342/357.01, 342/357.02, 342/357.03, 342/357.04, 342/357.12, 342/358, 342/357.16
• US Class Current: 701/213
• CPC Class Codes: G01S 19/235 Calibration of receiver components
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G04R 20/06 Decoding time data; Circuits therefor

Abstract

A method for minimizing time error uses a drift-susceptible time clock at the receiver carried by an asset to be tracked in a high-accuracy reduced-order GPS asset localization system. Long-term accuracy of the time clock is maintained by periodically re-synchronizing the clock with the master GPS time clock so that absolute asset time clock errors are kept below a known limit over the wide temperature ranges expected in the asset tracking application. This is accomplished with only a short GPS signal reception time; i.e., GPS frame synchronization and time-stamp decoding are not needed, and the asset position ambiguity associated with using GPS data-bit or code-bit edges as signal time references is eliminated.

Claims

1. A method for implementing a signal processing system that lessens time error in a Global Positioning System (GPS) receiver while using a time clock that is predisposed to drift in the GPS receiver, said method comprising the steps of:

receiving, at the GPS receiver, sequences of data bits from a GPS satellite transmitter;

detecting candidate word-alignment positions in the received data bit sequences;

selecting one of said candidate word-alignment positions as being correct; and

synchronizing the time clock with the time of transmission associated with the selected word-alignment position.

2. The method of claim 1 wherein the step of selecting one of said word alignment positions as being correct comprises the steps of:

examining one of said received data bit sequences to identify an alignment indication beginning with an arbitrarily assigned first bit;

repeating the step of examining one of said received data bit sequences, beginning with a bit subsequent to said first bit and continuing until all different ones of said data bit sequences have been examined;

for each repeated step of examining, checking the received data bit sequence extant thereat for a parity match and ignoring any alignment detection for which a calculated parity does not match a received parity; and

providing, as an output signal, a bit position that aligns with word boundaries in the received data bits for which a parity check matches.

3. The method of claim 1 wherein the step of detecting a word alignment of received data bits comprises:

examining, for an alignment indication, an arbitrarily selected thirty successive ones of the received data bits beginning with a first bit (i=1); and

repeating the step of examining thirty successive ones of the received data bits beginning with the second bit (i=2) and continuing through beginning with the thirtieth bit (i=30) until a unique correct alignment grid among the number of candidate grids (k=30) is established.

4. The method of claim 3 wherein the step of examining, for an alignment indication, an arbitrarily selected thirty successive ones of the received data bits comprises setting i=1, k=1 and the number of candidate grids to 30, and the step of repeating the step of examining thirty successive ones of the received data bits comprises:

a) examining for a parity match said arbitrarily selected thirty successive ones of the received data bits and eliminating the corresponding grid k=1 as being stale if calculated parity fails to match the received parity bits;

b) decreasing the candidate grid count by one; and

c) repeating step (a) for each of the other grids (k=2 through k=30) and, as each grid is eliminated for failure of parity bit match, decreasing the count of candidate grids by 1 until only one grid is left that is not stale, whereby the one grid that remains aligned with boundaries of the word in the received data bits is accepted as being true.

5. The method of claim 3 including the steps of:

monitoring bit erasures at the receiver; and

preventing elimination of any specific candidate grid if a bit erasure is detected within the 30 bit sequence being examined.

6. The method of claim 5 wherein the step of monitoring bit erasures at the receiver comprises monitoring received energy at the receiver in order to detect a drop in said received energy when an erasure occurs.

7. The method of claim 1 wherein the step of selecting one of said word alignment positions as being correct comprises the steps of:

examining one of said received data bit sequences to identify a word alignment indication beginning with an arbitrarily assigned first bit;

repeating the step of examining one of said received data bit sequences, beginning with a bit subsequent to said first bit and continuing until one word alignment grid position has occurred a number of times more often than all other candidate grid positions by a predetermined amount;

maintaining a score corresponding to the number of times each candidate grid position has occurred;

for each repeated step of examining, checking the received data bit sequence extant thereat for a parity match and increasing the score of any word alignment detections for which a calculated parity matches a received parity; and

providing, as an output signal, a bit position that aligns with word boundaries in the received data bits for which the score is the highest and in excess of the score of the next highest word alignment detections by a predetermined quality criterion.

8. A method for implementing a signal processing procedure that lessens time error in a Global Positioning System (GPS) receiver carried on an asset whose position is to be monitored, said receiver including an asset clock that is predisposed to drift, said method comprising the steps of:

receiving, at the GPS receiver, sequences of data bits from a GPS satellite transmitter;

synchronizing the asset clock using periodic correlation every 30 bits in the signal received from said GPS satellite transmitter;

using said periodic correlation to establish an intermediate time grid with which all asset clock measurements and clock synchronizations are aligned;

keeping track of the absolute bit count and time associated with each intermediate grid point at both said asset and a central station; and

limiting time measurements only to established intermediate grid points so as to allow the correct position of said asset to be calculated at said control station.

9. The method of claim 8 wherein said receiver is activated only when a position fix is needed.

10. A word alignment detector for use in a Global Positioning System (GPS) receiver carried on an asset where position is to be monitored, comprising:

a data shift register for receiving, serially, a stream of data bits transmitted from a GPS satellite, said stream of data bits including 6 parity bits;

a parity generator for producing a word segment comprised of parity bits;

a comparator responsive to said shift register and said parity generator for comparing the word segment produced by said parity generator with parity bits assumed to be stored in said shift register; and

a word alignment indicator responsive to said comparator for producing an indication that the last data bit to enter the shift register is the end of a 30 bit data word whenever the parity bits assumed to be stored in the shift register form a word segment equal to the word segment of parity bits produced by the parity generator.