System and method for encoding data to reduce power and time required to write the encoded data to a flash memory

• US 6,292,868 B1
• Filed: 09/03/1998
• Issued: 09/18/2001
• Est. Priority Date: 10/15/1996
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Norman, Robert D.
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US09/146,508
• Time in Patent Office: 1,111 Days
• Field of Search: 711/103, 365/202, 365/900, 365/230.03, 365/185.18, 365/230.01, 713/320
• US Class Current: 711/103
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method and system in which X-bit packets of bits (where X is an integer) are encoded to generate X-bit packets of encoded bits for writing to erased cells of a flash memory array, where less power is consumed to write a bit having a first value to an erased cell than to write a bit having a second value to the cell. Preferably, a count signal is generated for each packet of raw bits indicating the number of bits of the packet having the first (or second) value, the count signal is processed to generate a control signal which determines an encoding for the packet, and the raw bits of the packet are encoded according to a scheme determined by the control signal. In some embodiments, each erased cell is indicative of the binary value “1”, the count signal is compared to a reference value (indicative of X/2) to generate a control signal determining whether the packet should undergo polarity inversion, and the packet is inverted (or not inverted) depending on the value of the control signal. In alternative embodiments, a count signal is generated for each packet of bits to be written to erased cells of an array (where the count signal indicates the number of bits in the packet having a particular value), and each packet is encoded in a manner determined by the corresponding count signal to reduce the power needed to write the encoded bits to the erased cells. Preferably, flag bits indicative of the encoding of each packet are generated, and the flag bits (as well as the encoded packets) are stored in cells of the flash memory array.

Claims

1. A memory a device comprising:

an array of memory cells adapted to store data, the memory cells are pre-programmed to one of two binary data states;

control circuitry for receiving a plurality of packets of data bits, each of the packets includes a plurality of subsets of data bits to be written to the memory cells, the control circuitry analyses the plurality of subsets of data bits by accumulating data from each of the subsets using an accumulator, the control circuit also generates a count signal for each of the packets using a count generation circuit, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine a number of the bits of each of the packet having a second binary state; and

encoding circuitry to perform an encoding operation on each of the packets, wherein the encoding operation is selected from at least two different encoding states, wherein the encoding states is based on the count signal of each of the packets, wherein the encoding operation is performed to produce encoded data bits for each of the packets, and to invert a binary state of data bits of a packet if more than half of the data bits of the packet has the second binary state.

2. The memory device of claim 1 further comprising erase circuitry for pre-programming the memory cells to the first binary state.

3. The memory device of claim 1 further comprising a register for storing data indicating if the encoding circuitry inverted the plurality of data bits.

4. The memory device of claim 1 wherein the first binary state is a one.

5. The memory device of claim 1 wherein the memory cells are floating gate transistors, and the two binary data states are programmed by adjusting a voltage stored on the floating gate.

6. The memory device of claim 1 wherein the plurality of data bits is equal to a row of memory cells of the array.

7. The memory device of claim 1 further comprising a charge pump circuit for providing a programming voltage to program the memory cells to a second binary state.

8. A memory a device comprising:

an array of memory cells adapted to store data as either a binary one or a binary zero;

control circuitry for receiving a plurality of packets of input data bits to be written to the memory cells, each of the packets includes a plurality of subsets of data bits, the control circuitry adapted to analyze the plurality of the subsets of data bits by accumulating data from each of the subsets using an accumulator, the control circuit also generates a count signal for each of the packets using a count generation circuit, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine a number of binary zero input bits; and

encoding circuitry to perform an encoding operation on each of the packets, wherein the encoding operation is selected from at least two different encoding states, wherein the encoding states is based on the count signal of each of the packets, wherein the encoding operation is performed to produce encoded data bits for each of the packets, and to invert a binary state of data bits of a packet if more than half of the data bits of the packet are binary zero input bits.

9. The memory device of claim 8 further comprising erase circuitry for pre-programming the memory cells to the binary one state.

10. The memory device of claim 8 further comprising a register for storing data indicating if the encoding circuitry inverted the plurality of input data bits.

11. The memory device of claim 8 wherein the memory cells are floating gate transistors, and the two binary data states are programmed by adjusting a voltage stored on the floating gate.

12. A memory a device comprising:

an array of memory cells adapted to store data as either a binary one or a binary zero;

control circuitry for receiving a plurality of packets of input data bits to be written to the memory cells, each of the packets includes a plurality of subsets of data bits, the control circuitry adapted to analyze the plurality of the subsets of data bits by accumulating data from each of the subsets using an accumulator, the control circuit also generates a count signal for each of the packets using a count generation circuit, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine a number of binary one input bits; and

encoding circuitry to perform an encoding operation on each of the packets, wherein the encoding operation is selected from at least two different encoding states, wherein the encoding states is based on the count signal of each of the packets, wherein the encoding operation is performed to produce encoded data bits for each of the packets, and to invert a binary state of data bits of a packet if more than half of the data bits of the packet are binary one input bits.

13. The memory device of claim 12 further comprising erase circuitry for pre-programming the memory cells to the binary zero state.

14. A memory a device comprising:

an array of floating gate transistor memory cells adapted to store data as either a binary one or a binary zero by adjusting a voltage stored on the floating gate;

control circuitry for receiving a plurality of packets of input data bits to be written to the memory cells, each of the packets includes a plurality of subsets of data bits, the control circuitry adapted to analyze the plurality of the subsets of data bits by accumulating data from each of the subsets using an accumulator, the control circuit also generates a count signal for each of the packets using a count generation circuit, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine a number of binary zero input bits;

encoding circuitry to perform an encoding operation on each of the packets, wherein the encoding operation is selected from at least two different encoding states, wherein the encoding states is based on the count signal of each of the packets, wherein the encoding operation is performed to produce encoded data bits for each of the packets, and to invert a binary state of data bits of a packet if more than half of the data bits of the packet are binary zero input bits

erase circuitry for pre-programming the memory cells to the binary one state; and

a register for storing data indicating if the encoding circuitry inverted the plurality of input data bits.

15. A memory a device comprising:

an array of floating gate transistor memory cells adapted to store data as either a binary one or a binary zero by adjusting a voltage stored on the floating gate;

control circuitry for receiving a plurality of packets of input data bits to be written to the memory cells, each of the packets includes a plurality of subsets of data bits, the control circuitry adapted to analyze the plurality of the subsets of data bits by accumulating data from each of the subsets using an accumulator, the control circuit also generates a count signal for each of the packets using a count generation circuit, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine a number of binary one input bits;

encoding circuitry to perform an encoding operation on each of the packets, wherein the encoding operation is selected from at least two different encoding states, wherein the encoding states is based on the count signal of each of the packets, wherein the encoding operation is performed to produce encoded data bits for each of the packets, and to invert a binary state of data bits of a packet if more than half of the data bits of the packet are binary one input bits;

erase circuitry for pre-programming the memory cells to the binary zero state; and

a register for storing data indicating if the encoding circuitry inverted the plurality of input data bits.

16. A processing system comprising:

a memory controller; and

a flash memory device comprising;

an array of floating gate transistor memory cells adapted to store data as either a binary one or a binary zero by adjusting a voltage stored on the floating gate;

control circuitry for receiving a plurality of packets of input data bits to be written to the memory cells, each of the packets includes a plurality of subsets of data bits, the control circuitry adapted to analyze the plurality of the subsets of data bits by accumulating data from each of the subsets using an accumulator, the control circuit also generates a count signal for each of the packets using a count generation circuit, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine a number of binary one input bits;

encoding circuitry to perform an encoding operation on each of the packets, wherein the encoding operation is selected from at least two different encoding states, wherein the encoding states is based on the count signal of each of the packets, wherein the encoding operation is performed to produce encoded data bits for each of the packets, and to invert a binary state of data bits of a packet if more than half of the data bits of the packet are binary one input bits;

erase circuitry for pre-programming the memory cells to the binary one state; and

a register for storing data indicating if the encoding circuitry inverted the plurality of input data bits.

17. A method of writing data to a memory device, the method comprising:

receiving a plurality of packets of input data bits, each of the packets includes a plurality of subsets of input data bits, each bit encoded as either a binary one or a binary zero state;

analyzing each of the subsets of input data bits, wherein analyzing includes;

accumulating data from each of the subsets;

generating a count signal for each of the packets, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine if more than half of the input data bits of each of the packets are encoded as a binary zero; and

encoding each of the packets based to produce encoded data bits for each of the packets;

inverting the input data bits of a subset if more than half of the input data bits within that subset are encoded as a binary zero, such that the inverted input data bits have more than half of the input data bits are encoded as a binary one; and

storing the inverted input data bits in memory cells.

18. The method of claim 17 further comprising pre-programming the memory cells to a binary one.

19. The method of claim 17 further comprising storing data in a register to indicate that the input data bits were inverted.

20. A method of writing data to a memory device, the method comprising:

pre-programming memory cells to a binary zero;

receiving a plurality of packets of input data bits, each of the packets includes a plurality of subsets of input data bits, each bit encoded as either a binary one or a binary zero state;

analyzing each of the subsets of input data bits, wherein analyzing includes;

accumulating data from each of the subsets;

generating a count signal for each of the packets, wherein the count signal is generated based on the accumulated data of the subsets, wherein the count signal is used to determine if more than half of the input data bits of each of the packets are encoded as a binary one; and

encoding each of the packets based to produce encoded data bits for each of the packet;

inverting the input data bits of a subset if more than half of the input data bits within that subset are encoded as a binary one, such that the inverted input data bits have more than half of the input data bits are encoded as a binary zero; and

storing the inverted input data bits in memory cells.

21. A method of writing data packets to a non-volatile memory device, the method comprising:

selecting a plurality of the packets, wherein each of the packets comprising X binary bits;

determining a number of bits of the X binary bits in each of the plurality of packets which have a first data value wherein determining includes;

accumulating data from subsets of each of packets;

generating a count signal for each of the packets, wherein the count signal is generated based on the accumulated data of the subsets;

encoding each of the packets with encoded data bits based on the count signal of each of the packets, wherein encoding includes;

inverting the X binary bits in each of the plurality of packets to a second data value if the number of bits of the first data value exceeds a predetermined percentage of the X binary bits; and

writing the inverted X binary bits to the memory device.

22. The method of claim 21 wherein the predetermined percentage of the X binary bits is fifty percent (50%).

23. The method of claim 21 further comprising erasing the memory device such that memory cells of the memory array are programmed to the second data value.

24. The method of claim 21 further comprising:

generating a polarity flag for the inverted X binary bits, wherein the polarity flag includes a set of at least one polarity flag bit indicating that the X binary bits were inverted.