Dual-ported electronic random access memory that does not introduce additional wait states and that does not cause retransmission of data during shared access

• US 6,292,873 B1
• Filed: 05/22/1998
• Issued: 09/18/2001
• Est. Priority Date: 05/22/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Cross, Donald M., Keaveny, Thomas A.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US09/083,957
• Time in Patent Office: 1,215 Days
• Field of Search: 711/149, 711/154
• US Class Current: 711/149
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A high-performance dual-ported shared memory that interconnects two 32-bit PCI buses with a RAM memory that provides an address space of 64-bit words. The high-performance dual-ported shared memory provides two independent channels for reading from, and writing to, the RAM memory. By interleaving 64-bit read and write operations directed to the RAM memory with 32-bit PCI bus data transfer operations, and by internally buffering data, the high-performance dual-ported shared memory can independently provide data access at PCI data transfer rates to both PCI buses without introducing wait states.

Claims

1. A high-performance dual-ported shared memory that provides independent storage and retrieval operations on blocks of computer words to a first computer bus and to a second computer bus without introducing wait states in either computer bus following initiation of a storage or retrieval operation, both computer buses controlled by a clock and providing transfer of a computer word having a first width during each clock cycle, the high-performance dual-ported shared memory comprising:

a first port connected to the first computer bus;

a second port connected to the second computer bus;

a memory component that provides an address space of memory words having a second width equal to twice the first width; and

a multiplexer/demultiplexer component that combines pairs of computer words received from the first computer bus via the first port into memory words and that combines pairs of computer words received from the second computer bus via the second port into memory words for storage in the memory component and that separates memory words retrieved from the memory component into pairs of computer words, both computer words of each pair provided by the multiplexer/demultiplexer component to either the first or the second computer bus via the first or second port, the multiplexer/demultiplexer component buffering computer words so that, on each clock cycle, the multiplexer/demultiplexer component transfers a computer word to, or receives a computer word from, each computer bus and transfers a memory word to, or receives a memory word from, the memory component.

2. The high-performance dual-ported shared memory of claim 1 further including a memory bus that provides transfer of a memory word between the multiplexer/demultiplexer component and the memory component during each clock cycle.

3. The high-performance dual-ported shared memory of claim 1 wherein the multiplexer/demultiplexer component further comprises:

an address multiplexer/demultiplexer component that receives target computer bus addresses from the first and second computer buses via the first and second ports and translates the target computer bus addresses into target memory word addresses; and

a data multiplexer/demultiplexer component that

concurrently receives computer words from the from the first and second computer buses, buffers the received computer words in a write buffer corresponding to the first port and in a write buffer corresponding to the second port, combines pairs of buffered computer words into memory words, and provides the memory words to the memory component for storage at target memory addresses; and

receives memory words retrieved from target memory word addresses of the memory component, separates the received memory words into pairs of computer words, buffers the pairs of computer words in a read buffer corresponding to the first port and in a read buffer corresponding to the second port, and provides one computer word from the read buffer to each port during every clock cycle.

4. The high-performance dual-ported shared memory of claim 3 wherein the data multiplexer/demultiplexer component further comprises a first computer bus sequencer corresponding to the first computer bus and a second computer bus sequencer corresponding to the second computer bus, the first and second computer bus sequencers monitoring their corresponding computer buses to detect state changes in the computer buses and controlling read and write buffer operations in response to detected state changes.

5. The high-performance dual-ported shared memory of claim 3 wherein the address multiplexer/demultiplexer component further comprises:

a port selector that alternately asserts and deasserts a port selector signal to alternately select one of the two ports during each clock cycle, the memory component accessed for storing or retrieving a memory word on behalf of the computer bus associated with the selected port; and

first and second computer bus sequencers corresponding to the first and second computer buses, respectively, that monitor their corresponding computer buses to detect state changes in the computer buses and that control data exchanges between the read and write buffers, the computer buses, and the memory components in response to the detected state changes.

6. The high-performance dual-ported shared memory of claim 1 wherein computer words have a first width of 32 bits, wherein memory words have a second width of 64 bits, and wherein the read and write buffers each comprise 3 32-bit computer words.

7. The high-performance dual-ported shared memory of claim 1 wherein the computer buses are 32-bit PCI buses and the memory component comprises 4 2-megabyte static random access memory devices that together provide an 8-megabyte linear address space of 64-bit words.

8. A method for providing a memory that is independently and concurrently accessible to a number of computer buses, controlled by a clock, without introducing wait states during transfer of blocks of computer words to and from the memory, the method comprising:

for each of the number of computer buses, providing a port through which the computer bus accesses the memory by transmitting blocks of computer words to store in the memory and by retrieving blocks of computer words from the memory;

providing a memory that can store or retrieve, during each clock cycle, a memory word having a size in bits at least equal to the sum of the sizes of the computer words of the number of computer buses, a port selector that alternately selects a port for each clock cycle, and read and write buffers associated with each of the number of computer buses; and

during each clock cycle while the memory is concurrently accessed by the number of computer buses,

for each of the number of computer buses,

transferring a computer word between the computer bus and the read buffer or the write buffer associated with the computer bus; and

transferring a memory word between the memory and the read buffer or the write buffer associated with the computer bus that is associated with the port currently selected by the port selector.

9. The method of claim 8 further comprising:

while receiving a block of computer words from a computer bus to store in the memory starting at a target computer bus address,

translating the target computer bus address into a target memory address;

receiving a computer word from the port corresponding to the computer bus during each clock cycle and storing the computer word in the write buffer associated with the computer bus; and

when the port selector has currently selected the port corresponding to the computer bus, combining a number of computer words stored in the write buffer associated with the computer bus to form a memory word, writing the memory word to the target memory address, and incrementing the target memory address.

10. The method of claim 8 further including:

while retrieving a block of computer words from the memory for transmission to a computer bus starting at a target computer bus address,

translating the target computer bus address into a target memory address;

when the port selector has currently selected the port corresponding to the computer bus, retrieving a memory word from the target memory address, separating the memory word into a number of computer words, storing the number of computer words in the read buffer associated with the computer bus, and incrementing the target memory address; and

selecting the next computer word from the read buffer associated with the computer bus and providing the selected computer word to the computer bus via the port corresponding to the computer bus.

11. The method of claim 8 wherein an independently and concurrently accessible memory is provided to two computer buses that can each transfer a 32-bit computer word during each clock cycle, wherein the memory can store or retrieve, during each clock cycle, a 64-bit memory word, and wherein each read and write buffer comprises 3 32-bit computer words.

12. The method of claim 11 wherein, by storing 3 32-bit computer words in the read and write buffers, the read and write buffers provide buffering of at least one subsequent computer word following, in sequence, the computer word that is being transferred via a port to or from a computer bus, so that, when the computer bus introduces a wait cycle during the transfer of a block of computer words and then, on a subsequent clock cycle, continues the transfer of a block of computer words, the buffered computer word is immediately available to continue the transfer without introducing an additional wait cycle and without retransfer of already transferred computer words.

13. In a high-performance dual-ported shared memory that provides independent storage and retrieval operations on blocks of computer words to two computer buses, controlled by a clock, without introducing wait states in either computer bus following initiation of a storage or retrieval operation, a method for buffering and transferring computer words between the computer buses and the memory, the method comprising:

providing a memory component for storing memory words having a size in bits equal to at least the size of two computer words and providing buffers associated with each computer bus;

during concurrent transfer of blocks of computer words between the memory component and the two computer buses, transferring a computer word between each computer bus and the buffers associated with each computer bus and transferring a memory word between one of the two buffers and the memory component during each clock cycle; and

maintaining at least one subsequent computer word following, in sequence, the computer word that is being transferred to or from a computer bus, so that, when the computer bus introduces a wait cycle during the transfer of a block of computer words and then, on a subsequent clock cycle, continues the transfer of a block of computer words, the buffered subsequent computer word is immediately available to continue the transfer without introducing an additional wait cycle and without retransfer of already transferred computer words.

14. The method of claim 13 wherein, associated with each computer bus, are two buffers each comprising 3 computer words:

a read buffer including a head word, an even word, and an odd word; and

a write buffer comprising a copy word, an even word, and an odd word.

15. The method of claim 14 further including:

providing a selector that, on alternate clock cycles, selects a different computer bus; and

transferring a memory word between one of the two buffers associated with the selected computer bus and the memory component during each clock cycle.

16. The method of claim 15 for transferring a block of computer words from a computer bus to a position in the memory component staring at the first computer word within a memory word when the first computer word is available on the computer bus during a clock cycle in which the computer bus is selected, the method further comprising:

on the first clock cycle, transferring the first computer word of the block from the computer bus to the copy word of the write buffer; and

on subsequent clock cycles, repeating;

on the next clock cycle, copying the computer word in the copy word of the write buffer to the even word of the write buffer and transferring a computer word from the computer bus to the odd word of the write buffer; and

on the next clock cycle, combining the computer words in the even word of the write buffer and the odd word of the write buffer to form a memory word and transferring the memory word to the memory component and transferring a computer word from the computer bus to the copy word of the write buffer.

17. The method of claim 15 for transferring a block of computer words from a computer bus to a position in the memory component starting at the first computer word within a memory word when the first computer word is available on the computer bus during a clock cycle in which the computer bus is not selected further comprising:

on the first clock cycle, transferring the first computer word of the block from the computer bus to the copy word of the write buffer; and

on subsequent clock cycles, repeating;

on the next clock cycle, copying the computer word in the copy word of the write buffer to the even word of the write buffer, transferring a computer word from the computer bus to the odd word of the write buffer, combining the computer words in the even word of the write buffer and the odd word of the write buffer to form a memory word, and transferring the memory word to the memory component; and

on the next clock cycle, transferring a computer word from the computer bus to the copy word of the write buffer.

18. The method of claim 15 for transferring a block of computer words from a computer bus to a position in the memory component starting at the second computer word within a memory word when the first computer word is available on the computer bus during a clock cycle in which the computer bus is selected further comprising:

on the first clock cycle, transferring the first computer word of the block from the computer bus to the odd word of the write buffer;

on the second clock cycle, transferring the second computer word of the block from the computer bus to the copy word of the write buffer;

on the third clock cycle, transferring the first computer word of the block from the odd word of the write buffer to the second computer word within the starting memory word in the memory component, copying the second computer word from the copy word of the write buffer to the even word of the write buffer, and transferring the fourth computer word of the block from the computer bus to the odd word of the write buffer; and

on subsequent clock cycles, repeating;

on the next clock cycle, transferring a computer word from the computer bus to the copy word of the write buffer; and

on the next clock cycle, combining the computer words in the even word of the write buffer and the odd word of the write buffer to form a memory word, and transferring the memory word to the memory component, copying the computer word in the copy word of the write buffer to the even word of the write buffer, and transferring a computer word from the computer bus to the odd word of the write buffer.

19. The method of claim 15 for transferring a block of computer words from a computer bus to a position in the memory component starting at the second computer word within a memory word when the first computer word is available on the computer bus during a clock cycle in which the computer bus is not selected further comprising:

on the first clock cycle, transferring the first computer word of the block from the computer bus to the odd word of the write buffer;

on the second clock cycle, transferring the second computer word of the block from the computer bus to the copy word of the write buffer and transferring the first computer word of the block from the odd word of the write buffer to the second computer word within the starting memory word in the memory component; and

on subsequent clock cycles, repeating;

on the next clock cycle, transferring a computer word from the computer bus to the odd word of the write buffer and copying the computer word in the copy word of the write buffer to the even word of the write buffer; and

on the next clock cycle, combining the computer words in the even word of the write buffer and the odd word of the write buffer to form a memory word, transferring the memory word to the memory component, and transferring a computer word from the computer bus to the copy word of the write buffer.

20. The method of claim 15 for transferring a block of computer words from a position in the memory component starting at the first computer word within a memory word to a computer bus further comprising:

repeating, starting with a next clock cycle during which the computer bus is selected;

on the next clock cycle, retrieving a memory word from the memory component, separating the memory word into a first computer word and a second computer word, storing the first computer word in the head word of the read buffer and the even word of the read buffer, with the storing of the first computer word in the head word of the read buffer resulting in the transfer of the first computer word to the computer bus, and storing the second computer word in the odd word of the read buffer; and

on the next clock cycle, copying the computer word in the odd word of the read buffer into the head word of the read buffer, with the copying of the computer word in the odd word of the read buffer into the head word of the read buffer resulting in the transfer of the computer word copied to the head word of the read buffer to the computer bus.

21. The method of claim 15 wherein the 3 computer words comprising the read buffers are designated the head word of the read buffer, the even word of the read buffer, and the odd word of the read buffer, the method for transferring a block of computer words from a position in the memory component starting at the second computer word within a memory word to a computer bus further comprising:

on the next clock cycle during which the computer bus is selected, retrieving a memory word from the memory component, separating the memory word into a first computer word and a second computer word, storing the first computer word in the even word of the read buffer and the second computer word in the odd word of the read buffer; and

on subsequent clock cycles, repeating;

on the next clock cycle, copying the computer word in the odd word of the read buffer into the head word of the read buffer, with the copying of the computer word in the odd word of the read buffer into the head word of the read buffer resulting in the transfer of the computer word copied to the head word of the read buffer to the computer bus; and

on the next clock cycle, retrieving a memory word from the memory component, separating the memory word into a first computer word and a second computer word, storing the first computer word in the even word of the read buffer and the head word of the read buffer and storing the second computer word in the odd word of the read buffer, with the storing of the first computer word in the head word of the read buffer resulting in the transfer of the first computer word to the computer bus.