RTL analysis tool

• US 6,292,931 B1
• Filed: 02/20/1998
• Issued: 09/18/2001
• Est. Priority Date: 02/20/1998
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dupenloup, Guy
• Primary Examiner(s): Lintz, Paul R.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/027,520
• Time in Patent Office: 1,306 Days
• Field of Search: 395/500-2-5, 395/500-5-5, 395/705, 716/1-21, 703/14-16
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method of determining circuit characteristics of an integrated circuit design defined by RTL code, said method comprising the steps of identifying hardware elements in the RTL code, determining key pins for said identified hardware elements, and extracting critical design structure from the RTL code. The hardware elements identified include flipflops, latches, tristate buffers, bidirectional buffers and memories. The critical design structures include design hierarchy and nets, including clock nets, multiply-driven nets, reset nets, and RAM write enable nets.

Claims

1. A method of generating a synthesis script for synthesizing RTL code, said method comprising the steps of:

identifying hardware elements in the RTL code, said identified hardware elements having pins;

determining key pins for said identified hardware elements, wherein said key pins are pins of the identified hardware elements having active edges or active levels;

extracting critical design structure from the RTL code; and

generating a synthesis script for a synthesis tool to synthesize the RTL code based on said identified hardware elements, said key pins and said critical design structure.

2. The method of claim 1 wherein said hardware elements comprise flipflops.

3. The method of claim 2 wherein for each of said identified flipflops, the following properties of said identified flipflops are determined:

data input pin;

clock pin with active edge;

clear pin with active level; and

preset pin with active level.

4. The method of claim 1 wherein said critical design structures comprises design hierarchy and nets.

5. The method of claim 4 wherein said nets comprise:

clock nets;

multiply-driven nets;

reset nets; and

RAM write enable nets.

6. The method of claim 4 wherein said design hierarchy comprises:

hierarchical modules;

memories;

CoreWare cores and hard macros; and

instantiated technology cells.

7. The method of claim 1 wherein said critical design structures comprises clock domains and clock domain interfaces.

8. The method of claim 1 further comprising the step of determining hierarchy purity of modules of the IC design.

9. The method of claim 1 further comprising the step of identifying showstoppers for the purposes of modifying the IC design.

10. The method of claim 1 wherein said hardware elements comprise latches.

11. The method of claim 1 wherein said hardware elements comprise tristate buffers.

12. The method of claim 1 where in said hardware elements comprise bidirectional buffers.

13. The method of claim 1 wherein said hardware elements comprise memories.

14. The method of claim 1 wherein said key pins comprise data input pins.

15. The method of claim 1 wherein said key pins comprise clock pins with active edge.

16. The method of claim 1 wherein said key pins comprise clear pins with active level.

17. The method of claim 1 wherein said key pins comprise preset pins with active level.

18. The method of claim 1 wherein said critical design structure comprises a a design hierarchy.

19. The method of claim 1 wherein said critical design structure comprises a multiply-driven net.

20. The method of claim 1 wherein said critical design structure comprises a clock net.

21. The method of claim 1 wherein said critical design structure comprises a clock domain.

22. The method of claim 1 wherein said critical design structure comprises a clock domain interface.

23. The method of claim 1 wherein said critical design structure comprises a clock domain interface.

24. The method of claim 1 wherein said critical design structure comprises an asynchronous reset net.

25. The method of claim 1 wherein said critical design structure comprises a synchronous reset net.

26. The method of claim 1 wherein said critical design structure comprises a RAM write enable net.

27. The method of claim 1 wherein said critical design structure comprises a hierarchy purity of module.

28. The method of claim 1 wherein said critical design structure comprises pins driving each module output.

29. The method of claim 1 wherein said critical design structure comprises a logic surrounding memory.

30. The method of claim 1 wherein said critical design structure comprises a data bus.

31. A method according to claim 1 wherein the hardware elements are identified by identifying templates in the RTL code that indicate the presence of said elements.

32. An apparatus for generating a synthesis script for synthesizing RTL code, said apparatus comprising:

a processor; and

memory connected to said processor;

said memory having instructions for said processor to;

identify hardware elements in the RTL code, said identified hardware elements having pins;

determine key pins for said identified hardware elements, wherein said key pins are pins of the identified hardware elements having active edges or active levels;

extract critical design structure from the RTL code, and

generate a synthesis script for a synthesis tool to synthesize the RTL code based on said identified hardware elements, said key pins and said critical design structure.

33. An apparatus for generating a synthesis script for synthesizing RTL code, said apparatus comprising:

means for identifying hardware elements in the RTL code, said identified hardware elements having pins;

means for determining key pins for said identified hardware elements, wherein said key pins are pins of the identified hardware elements having active edges or active levels;

means for extracting critical design structure from the RTL code; and

means for generating a synthesis script for a synthesis tool to synthesize the RTL code based on said identified hardware elements, said key pins and said critical design structure.

34. A computer storage medium having instructions encoded thereon for synthesizing RTL code, said computer storage medium comprising:

a computer encoded instruction for identifying hardware elements in the RTL code, said identified hardware elements having pins;

a computer encoded instruction for determining key pins for said identified hardware elements, wherein said kev pins are pins of the identified hardware elements having active edges or active levels;

a computer encoded instruction for extracting critical design structure from the RTL code; and

a computer encoded instruction for generating a synthesis script for a synthesis tool to synthesize the RTL code based on said identified hardware elements, said key pins and said critical design structure.

35. A computer storage medium of claim 34 wherein said computer storage medium is selected from a group consisting of magnetic device, optical device, magneto-optical device, floppy diskette, CD-ROM, magnetic tape, computer hard drive, and memory card.