Method for making micro-mechanical semiconductor accelerometer

• US 6,294,400 B1
• Filed: 08/09/2000
• Issued: 09/25/2001
• Est. Priority Date: 07/31/1998
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Litton Systems Incorporated
• Inventors: Stewart, Robert E., Goldman, Arnold E.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/634,214
• Time in Patent Office: 412 Days
• Field of Search: 735/143.2, 735/141.8, 735/142.1, 735/142.3, 735/143.6, 438/50, 438/51, 438/52, 438/53, 257/254
• US Class Current: 438/52
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0828 the mass being of the paddle type being suspended at one of its longitudinal ends

Abstract

A precision, micro-mechanical semiconductor accelerometer of the differential-capacitor type comprises a pair of etched opposing cover layers fusion bonded to opposite sides of an etched proofmass layer to form a hermetically sealed assembly. The cover layers are formed from commercially available, Silicon-On-Insulator (“SOI”) wafers to significantly reduce cost and complexity of fabrication and assembly. The functional semiconductor parts of the accelerometer are dry-etched using the BOSCH method of reactive ion etching (“RIE”), thereby significantly reducing contamination inherent in prior art wet-etching processes, and resulting in features advantageously bounded by substantially vertical sidewalls.

Claims

1. A method for producing a semiconductor accelerometer of the differential capacitor type, comprising the steps of:

a) selecting a semiconductor proofmass wafer, and a pair of SOI wafers of the type that have an oxide layer between semiconductor handle and device layers;

b) fixing a first thickness of dielectric material on said opposite sides of each said SOI wafer;

c) fixing a second thickness of dielectric material on opposite sides of said proofmass wafer;

d) etching said device layer and said first thickness of dielectric material overlying said device layer of each said SOI wafer through to said underlying oxide layer to define on said device layer an associated central electrode and a continuous, marginal frame around said electrode;

e) etching said proofmass wafer and said second thicknesses of dielectric material on said opposite sides thereof to define within said wafer a central proofmass having opposite faces, a continuous, marginal frame around said proofmass and a flexible hinge connecting said proofmass to said frame;

f) assembling said proofmass wafer between opposed ones of said SOI wafers such that said frames of said wafers are in alignment, said proofmass is centered between and spaced apart from respective, opposed ones of said electrodes by a distance equal to the sum of said first and second thicknesses of dielectric material, and said proofmass is articulated to rotate between said electrodes at said hinge; and

then

g) bonding each said SOI wafer to a respective one of said opposed sides of said proofmass wafer such that a respective one of said first thicknesses of dielectric material on said frames around said electrodes is fused to a respective one of said second thicknesses of dielectric material on said opposed sides of said frame around said proofmass, thereby forming a hermetically sealed assembly.

2. A method as defined in claim 1 wherein the step of etching said proofmass wafer further comprises the step of etching a plurality of holes through said proofmass between said opposite sides thereof.

3. A method as defined in claim 1 wherein the steps of selectively etching said wafers to define said electrodes, said proofmass, said frames and said hinge further comprise the step of etching said features to include sidewalls substantially orthogonal to respective planes of said wafers.

4. A method as defined in claim 1 wherein the steps of etching said features further comprise the step of dry-etching said features by means of an RIE process.

5. A method as defined in claim 4 wherein the step of etching said features further comprises the step of etching said features by means of the BOSCH process.

6. A method as defined in claim 1 wherein the step of etching said device layer and said first thickness of dielectric material further includes the step of etching said oxide layer to said underlying handle layer.

7. A method as defined in claim 6 wherein the step of etching said oxide layer further includes the step of etching said oxide layer so that etched regions of said oxide layer extend beyond at least one sidewall of said electrode.

8. A method as defined in claim 6 wherein the step of etching said oxide layer further includes the step of etching said oxide layer so that etched regions of said oxide layer extend beyond at least one sidewall of said marginal frame.