Method of forming semiconductor device having a sub-chip-scale package structure

• US 6,294,405 B1
• Filed: 04/14/2000
• Issued: 09/25/2001
• Est. Priority Date: 12/01/1997
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Higgins, III, Leo M.
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Diaz, Jose R.
• Application Number:
  US09/550,482
• Time in Patent Office: 529 Days
• Field of Search: 257/782, 257/783, 438/108, 438/127, 438/612, 438/613
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/07811 Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A semiconductor device (1) has a sub-chip-scale package structure, wherein the substrate (50) has at least one of an X dimension and a Y dimension smaller than a corresponding dimension of the semiconductor die (10). The semiconductor device (1) has a plurality of electrical connections between the semiconductor die and the substrate, the electrical connections (15, 20) being provided within the outer periphery of the substrate. The semiconductor device (1) permits packaging of semiconductor die (10) at the wafer level, that is, before the semiconductor die are singulated.

Claims

1. A method of forming a semiconductor device comprising:

providing a wafer having a plurality of semiconductor die, each semiconductor die of the plurality of semiconductor die having a surface and outer periphery X and outer periphery Y dimensions, the outer periphery X and outer periphery Y dimensions of each semiconductor die being perpendicular to each other;

forming a plurality of electrical contacts on the surface of said each semiconductor die; and

overlying a plurality of package substrates over the plurality of semiconductor die, such that each package substrate of the plurality of package substrates is electrically connected to the plurality of electrical contacts of a respective semiconductor die of the plurality of semiconductor die, wherein;

said each package substrate has outer periphery X′ and

outer periphery Y′

dimensions being perpendicular to each other, and at least one of (i) the outer periphery X′

dimension of said each package substrate is less than the X dimension of said respective semiconductor die, and (ii) the outer periphery Y′

dimension of said each package substrate is less than the Y dimension of said respective semiconductor die.

2. The method of claim 1, wherein said each package substrate has an outer periphery, and the plurality of electrical contacts are located within the outer periphery of said each package substrate.

3. The method of claim 1, further comprising depositing an underfill encapsulation layer between said each package substrate and said each semiconductor die.

4. The method of claim 3, wherein said each semiconductor die has an outer peripheral surface, and the underfill encapsulation layer forms a fillet extending along the outer peripheral surface of said each semiconductor die.

5. The method of claim 1 further comprising singulating said respective semiconductor die after overlying.

6. The method of claim 1, wherein both (i) the outer periphery X′

dimension of said each package substrate is less than the outer periphery X dimension of said respective semiconductor die, and (ii) the outer periphery Y′

dimension of said each package substrate is less than the outer periphery Y dimension of said respective semiconductor die.

7. The method of claim 1, wherein the plurality of electrical contacts comprises metal bumps.

8. The method of claim 7, wherein the plurality of metal bumps comprises solder.

9. The method of claim 8, wherein overlying includes reflowing the solder such that said each package substrate is attached to said respective semiconductor die.

10. The method of claim 1, wherein said each package substrate includes an insulating layer having a first surface and a second surface opposite the first surface, a plurality of direct chip attach bond pads on the first surface, a plurality of ball grid array bond pads on the second surface, a plurality of electrical interconnections that interconnect the plurality of direct chip attach bond pads to the plurality of ball grid array bond pads, and a plurality of ball grid array balls respectively attached to the plurality of ball grid array bond pads.

11. The method of claim 10, wherein the plurality of ball grid array balls are attached to said each package substrate before overlying.

12. The method of claim 10, wherein the plurality of ball grid array balls are attached to said each package substrate after overlying.

13. The method of claim 10, wherein the plurality of electrical interconnections extend through said each package substrate.

14. The method of claim 1, further comprising singulating said respective semiconductor die after overlying, such that said each semiconductor die has an outer periphery, said each semiconductor die further comprising a plurality of contact pads arranged adjacent the outer periphery and a plurality of redistribution traces extending from the plurality of contact pads toward a central portion of said each semiconductor die.

15. The method of claim 1, wherein said each package substrate includes an insulating layer, the insulating layer comprising a material from a group consisting of organic polymer and ceramic.

16. The method of claim 15, wherein said material is an organic polymer.

17. A method of forming a semiconductor device comprising:

providing a semiconductor die having a surface, and outer periphery X and outer periphery Y dimensions, the outer periphery X and outer periphery Y dimensions of the semiconductor die being perpendicular to each other;

forming a plurality of electrical contacts on the surface of the semiconductor die; and

overlying a package substrate over the semiconductor die such that the package substrate is electrically connected to the plurality of electrical contacts, wherein;

the package substrate has outer periphery X′ and

outer periphery Y′

dimensions being perpendicular to each other, at least one of (i) the outer periphery X′

dimension of the package substrate is less than the outer periphery X dimension of the semiconductor die, and (ii) the outer periphery Y′

dimension of the package substrate is less than the outer periphery Y dimension of the semiconductor die, the package substrate has an outer periphery, and the plurality of electrical contacts are located within the outer periphery X dimension and outer periphery Y dimension of the package substrate.

18. A method of forming a semiconductor device comprising:

forming a semiconductor die having a surface, and X and Y dimensions, the X and Y dimensions of the semiconductor die being perpendicular to each other;

forming a plurality of electrical contacts on the surface of the semiconductor die; and

attaching the semiconductor device to a substrate, wherein the substrate has a plurality of electrical connections between conductive portions of a first outer surface and conductive portions of a second outer surface, the first outer surface is between and adjacent to the second outer surface and the surface of the semiconductor die, wherein one of the plurality of electrical connections of the substrate is electrically connected to at least one of the plurality of electrical contacts on the surface of the semiconductor die, wherein the first outer surface of the substrate has X′ and

Y′

dimensions being perpendicular to each other, and at least one of (i) the X′

dimension of the first outer surface substrate is less than the X dimension of the semiconductor die, and (ii) the Y′

dimension of the first outer surface substrate is less than the Y dimension of the semiconductor die, furthermore, the substrate has an outer periphery, and the plurality of electrical contacts are located within the outer periphery of the substrate.

19. The method of claim 18, wherein the plurality of electrical contacts comprises metal bumps.

20. The method of claim 19, wherein the plurality of metal bumps comprises solder.

21. The method of claim 18, further comprising an underfill encapsulation layer between the semiconductor die and the substrate.

22. The method of claim 21, wherein both (i) the X′

dimension of the substrate is less than the X dimension of the semiconductor die, and (ii) the Y′

dimension of the substrate is less than the Y dimension of the semiconductor die.

23. The method of claim 21, wherein the substrate has an outer peripheral surface, and the underfill encapsulation layer forms a fillet extending along the outer peripheral surface of the substrate.