Structure and method for improved latch-up using dual depth STI with impurity implant

• US 6,294,419 B1
• Filed: 11/06/2000
• Issued: 09/25/2001
• Est. Priority Date: 04/30/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven Howard, Gauthier, Robert J. Jr., Mann, Randy William, Brown, Jeffrey Scott
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Jones, Josetta I
• Application Number:
  US09/705,882
• Time in Patent Office: 323 Days
• Field of Search: 438/296, 438/221, 438/223, 438/424, 438/427, 438/433
• US Class Current: 438/221
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.

Claims

1. A method for making a dual depth trench, the method comprising:

a) providing a substrate having at least one dielectric layer thereon and a resist layer on said dielectric layer;

b) patterning said resist layer and forming a trench through said at least one dielectric layer into said substrate according to said patterned resist layer;

c) implanting a dopant into said substrate using said patterned resist layer as a mask for forming a doped region in said substrate below said trench;

d) removing said resist and said at least one dielectric layer adjacent said trench;

e) etching said substrate exposed by step d) simultaneously with said trench until a bottom of said trench reaches said doped region for forming a dual depth trench;

f) filling said dual depth trench; and

g) implanting wells of opposite conductivity types into said substrate on opposite sides of said dual depth trench.

2. The method of claim 1 wherein in step b), said trench is formed to a depth of about 0.25-0.35 microns.

3. The method of claim 1, wherein said doped region abuts both said first and second wells.

4. The device of claim 1 wherein said wells are formed deeper in said substrate than said dual depth trench.

5. The method of claim 1 wherein said first well and second wells extends laterally under said doped region.

6. The method of claim 1 wherein one of said wells extends under a minority of said impurity region.

7. The method of claim 1 wherein said doped region is self-aligned with sides of said trench.

8. The method of claim 1 further comprising the step of:

forming well edge implants adjacent to said dual depth trench in said wells.

9. The method of claim 8 wherein said well edge implants are highly doped areas of the same conductivity type on their respective wells.

10. The method of claim 8 wherein said well edge implants are formed under a STI region.

11. A method of forming a semiconductor device comprising:

a) providing a substrate;

b) depositing a hybrid resist on said substrate;

c) exposing said hybrid resist through a mask containing a plurality of shapes, wherein portions of said hybrid resist blocked by said mask shapes are unexposed, portions of said hybrid resist not blocked by said mask are fully exposed and transition areas of said hybrid resist under mask shape edges are exposed with an intermediate exposure;

d) developing said hybrid resist such that portions of said hybrid resist which were exposed to intermediate amounts of exposure are removed thereby forming a plurality of well edge spaces;

e) etching said substrate according to said patterned hybrid resist to form a first trench;

f) implanting a dopant into said substrate below said first trench using said patterned hybrid resist as a mask;

g) removing said hybrid resist adjacent said first trench;

h) etching said substrate exposed by step g) simultaneously with said first trench until a bottom of said first trench reaches said doped region for forming a dual depth trench;

i) filling said dual depth trench; and

j) implanting wells of opposite conductivity types into said substrate on opposite sides of said dual depth trench.

12. The method of claim 11 wherein step j) comprises:

j1) depositing a second hybrid resist on said substrate;

j2) exposing said hybrid resist through a mask containing a plurality of shapes, wherein portions of said hybrid resist blocked by said mask shapes are unexposed, portions of said hybrid resist not blocked by said mask are fully exposed and transition areas of hybrid resist under mask shape edges are exposed with an intermediate exposure;

j3) developing said hybrid resist whereby at least one well space in said hybrid resist is opened; and

j4) forming at least one well region in said substrate through said at least one well space in said hybrid resist.

13. The method of claim 12 further comprising the steps of:

before said step, j3) developing said second hybrid resist such that portions of said hybrid resist which were exposed to intermediate amounts of exposure are removed forming a plurality of well edge spaces; and

forming a plurality of well edge implants in said substrate through said well edge spaces.

14. The method of claim 13 wherein at least one of said plurality of well edge implants is formed under a shallow trench isolation.

15. A method for making a dual depth trench, the method comprising:

a) providing a substrate having a resist layer thereon;

b) patterning said resist layer and forming a trench into said substrate according to said patterned resist layer;

c) implanting a dopant into said substrate using said patterned resist layer as a mask for forming a doped region in said substrate below said trench;

d) removing said resist adjacent said trench;

e) etching said substrate exposed by step d) simultaneously with said trench until a bottom of said trench reaches said doped region for forming a dual depth trench;

f) filling said dual depth trench; and

g) implanting wells of opposite conductivity types into said substrate on opposite sides of said dual depth trench.

16. The method of claim 15 wherein said doped region has a peak approximately 0.75-0.85 microns into said substrate.

17. A semiconductor device made by the method of claim 15.