Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device

• US 6,294,434 B1
• Filed: 09/27/2000
• Issued: 09/25/2001
• Est. Priority Date: 09/27/2000
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Tseng, Horng-Huei
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/670,379
• Time in Patent Office: 363 Days
• Field of Search: 438/301, 438/303, 438/523, 438/533, 438/586, 438/592, 438/664
• US Class Current: 438/303
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/28044 the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A process of forming a metal silicide layer, for a salicide gate structure, and forming a metal silicide layer for a MOSFET source/drain region, featuring ion implanted metal ions providing the metal component of the metal silicide layers, has been developed. After formation of a polysilicon gate structure, and of a heavily doped source/drain region, metal ions are implanted into a top portion of both the heavily doped source/drain region, and polysilicon gate structure. The metal ions are chosen from a group that includes titanium, tantalum, platinum, palladium, nickel and cobalt ions. A first anneal procedure is then employed resulting in the formation of the metal silicide layer on the heavily doped source/drain region, and formation of a salicide gate structure, comprised of metal silicide on the polysilicon gate structure. Selective removal of unreacted metal ions is then accomplished using wet etchant solutions, followed by a second anneal procedure, used to reduce the resistance of the metal silicide layers. The use of implanted metal ions, when compared to a blanket deposited metal layer, reduces the risk of unremoved metal, or formation of metal silicide ribbons, located on the surface of insulator, at the conclusion of the selective removal procedure, resulting in gate to substrate leakage or shorts.

Claims

1. A method of fabricating a metal oxide semiconductor field effect transistor (MOSFET), device on a semiconductor substrate, comprising the steps of:

forming a gate insulator layer on said semiconductor substrate;

forming a gate structure on said gate insulator layer;

forming insulator spacers on the sides of said gate structure;

forming a heavily doped source/drain region in an area of said semiconductor substrate not covered by said gate structure or by said insulator spacers;

performing a blanket ion implantation procedure to place metal ions into a top portion of said heavily doped source/drain region, and into a top portion of said gate structure;

performing a first anneal procedure to form first metal silicide layers on the top surface of said heavily doped source/drain region, and to form a second metal silicide layer on the top surface of said gate structure, resulting in a salicide gate structure comprised of said second metal silicide layer, on underlying, said gate structure, leaving unreacted metal ions located on said insulator spacers;

selectively removing said unreacted metal ions; and

performing a second anneal cycle to convert said first metal silicide layers, and said second metal silicide layer, to lower resistance, metal silicide layers.

2. The method of claim 1, wherein said gate insulator is a silicon dioxide layer, at a thickness between about 50 to 300 Angstroms, obtained via thermal oxidation procedures, performed in an oxygen-steam ambient at a temperature between about 800 to 1200°

C.

3. The method of claim 1, wherein said gate structure is formed from a polysilicon layer, obtained via LPCVD procedures at a thickness between about 500 to 3500 Angstroms, and either in situ doped during deposition via the addition of arsine or phosphine to a silane ambient, or deposited intrinsically then doped via implantation of arsenic or phosphorous ions.

4. The method of claim 1, wherein said insulator spacers are comprised of silicon oxide, or silicon nitride, obtained via LPCVD or PECVD procedures, at a thickness between about 500 to 3000 Angstroms, then defined via an anisotropic RIE procedure using CF₄ or CHF₃ as an etchant.

5. The method of claim 1, wherein said heavily doped source/drain region is formed via ion implantation of arsenic or phosphorous ions, at an energy between about 30 to 70 KeV, at a dose between about 10¹⁴ to 10¹⁵ atoms/cm².

6. The method of claim 1, wherein said metal ions are chosen from a group consisting of titanium, tantalum, platinum, palladium, nickel, and cobalt, obtained via ion implantation procedures performed using an implant angle between about 0 to 20 degrees.

7. The method of claim 1, wherein said first metal silicide layers, located on said heavily doped source/drain region, are formed to a thickness between about 30 to 1000 Angstroms, via a rapid thermal anneal procedure, performed in a nitrogen ambient.

8. The method of claim 1, wherein said second metal silicide layer, located on said gate structure, is formed at a thickness between about 30 to 1000 Angstroms, via a rapid thermal anneal procedure, performed in a nitrogen ambient.

9. The method of claim 1, wherein said unreacted metal ions are selectively removed in a solution comprised of H₂O₂—

NH₄OH—

H₂O, at a temperature between about 60 to 100°

C.

10. The method of claim 1, wherein said second anneal cycle, used to convert said first metal silicide layers, and said second metal silicide layer, to said lower resistance metal silicide layer, is performed using a rapid thermal anneal procedure, in a nitrogen ambient.

11. A method of forming a metal silicide layer, on a MOSFET source/drain region, and on a MOSFET gate structure, on a semiconductor substrate, featuring a blanket ion implantation procedure to supply the metal component of the metal silicide layers, anneal cycles to convert implanted metal ions to said metal silicide layer, and to selectively remove unreacted metal ions, comprising the steps of:

providing a polysilicon gate structure on an underlying silicon dioxide gate insulator layer, with insulator spacers located on the sides of said polysilicon gate structure, and with a heavily doped source/drain region located in a region of said semiconductor substrate not covered by said polysilicon gate structure, or by said insulator spacers;

performing said blanket ion implantation procedure, at an implant angle between about 0 to 20°

, to place said metal ions into a top portion of said heavily doped source/drain region, into a top portion of said polysilicon gate structure, and into said insulator spacers;

performing a first rapid thermal anneal procedure to form first metal silicide layers on said heavily doped source/drain region, and to form a second metal silicide layer on said polysilicon gate structure, resulting in a salicide gate structure comprised of said second metal silicide layer on said polysilicon gate structure, while leaving said metal ions in said insulator spacers unreacted;

selectively removing said unreacted metal ions from said insulator layer, via use of a solution comprised of H₂O₂—

NH₄OH—

H₂O, at a temperature between about 60 to 100°

C.; and

performing a second rapid thermal anneal procedure to convert said first metal silicide layers and said second metal silicide layer, to lower resistance metal silicide layers.

12. The method of claim 11, wherein said silicon dioxide gate insulator layer is grown to a thickness between about 50 to 300 Angstrom, via thermal oxidation procedures, performed in an oxygen-steam ambient at a temperature between about 800 to 1200°

C.

13. The method of claim 11, wherein said polysilicon gate structure is formed from a polysilicon layer, obtained via LPCVD procedures at a thickness between about 500 to 3500 Angstroms.

14. The method of claim 11, wherein said insulator spacers are comprised of silicon oxide, or silicon nitride, obtained via LPCVD or PECVD procedures, at a thickness between about 500 to 3000 Angstroms, then defined via an anisotropic RIE procedure using CF₄ or CHF₃ as an etchant.

15. The method of claim 11, wherein said heavily doped source/drain region is formed via ion implantation of arsenic or phosphorous ions, at an energy between about 30 to 70 KeV, and at a dose between about 10¹⁴ to 10¹⁵ atoms/cm².

16. The method of claim 11, wherein said metal ions are chosen from a group consisting of titanium, tantalum, platinum, palladium, nickel, and cobalt.

17. The method of claim 11, wherein said first rapid thermal anneal procedure, used to form said first metal silicide layers on said heavily doped source/drain region, and to form said second metal silicide layer on said polysilicon gate structure, is performed in a nitrogen ambient.

18. The method of claim 11, wherein said first metal silicide layers, and said second metal silicide layer, are formed to a thickness between about 30 to 70 Angstroms.

19. The method of claim 11, wherein said second rapid thermal anneal procedure, used to convert said first metal silicide layers, and said second metal silicide layer, to lower resistance metal silicide layers is performed in a nitrogen ambient.