Manufacturing method of interconnection layer for semiconductor device

• US 6,294,462 B1
• Filed: 08/04/1998
• Issued: 09/25/2001
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Rha, Sa Kyun
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US09/129,000
• Time in Patent Office: 1,148 Days
• Field of Search: 438/618, 438/622, 438/637, 438/641, 438/643, 438/653, 438/674, 438/679, 438/680, 438/681, 438/687, 438/627
• US Class Current: 438/641
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate, forming an insulation layer on a surface of the conductive pattern, forming grooves in the insulation layer exposing portions of the conductive pattern, forming a first barrier layer pattern on an upper surface of the insulation layer and on sidewalls and bottoms of each of the grooves, selectively forming a seed layer on portions of the first barrier layer pattern, selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer, and forming a second barrier layer on an upper surface and sides of the copper interconnection layer.

Claims

1. A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of:

forming a conductive pattern near a surface of a semiconductor substrate or on the surface of the semiconductor substrate;

forming an insulation layer on a surface of the conductive pattern;

forming cavities in the insulation layer exposing portions of the conductive pattern;

forming a first barrier layer pattern on a surface of the insulation layer and on sidewalls and bottoms of each of the cavities;

selectively forming a seed layer directly on and in contact with portions of the first barrier layer pattern formed on the sidewalls and bottoms of the grooves;

selectively forming a copper interconnection layer on the first barrier layer pattern and the seed layer; and

forming a second barrier layer on an upper surface and sides of the copper interconnection layer.

2. The method of claim 1, wherein the step of forming the conductive pattern forms a diffusion layer in the semiconductor substrate.

3. The method of claim 2, wherein the step of forming the conductive pattern forms a metal interconnection connected to the diffusion layer.

4. The method of claim 1, wherein the step of forming the conductive pattern forms a gate electrode on the surface of the semiconductor substrate.

5. The method of claim 4, wherein the step of forming the conductive pattern forms a metal interconnection connected to the gate electrode.

6. The method of claim 1, wherein the step of forming the conductive pattern forms a bit line on the surface of the semiconductor substrate.

7. The method of claim 6, wherein the step of forming the conductive pattern also forms a metal interconnection connected to the bit line.

8. The method of claim 1, wherein the step of selectively forming the seed layer forms a layer of at least one of nitrated titanium, tungsten, and copper.

9. The method of claim 8, wherein the step of selectively forming the seed layer forms a layer having a thickness of 500 Å

or less.

10. The method of claim 1, wherein the step of forming the first barrier layer pattern forms a layer of at least one of Ti, TiN, TaN, TiW, TaW, TiSi_xY_y and TaSi_xY_n.

11. The method of claim 1, wherein the step of forming the first barrier layer pattern forms two sequentially stacked films each including one of Ti, TiN, TaN, TiW, TaW, TiSi_xY_y and TaSi_xY_n.

12. The method of claim 1, wherein the step of forming the second barrier layer forms a film of at least one of Ti, TiN, TaN, TiW, TaW, TiSi_xY_y and TaSi_xY_n.

13. The method of claim 1, wherein the step of forming the second barrier layer pattern forms two sequentially stacked films each including one of Ti, TiN, TaN, TiW, TaW, TiSi_xY_y and TaSi_xY_n films.

14. The method of claim 1, wherein the step of forming grooves in the insulation layer includes a step of dry etching the insulation layer.

15. The method of claim 1, wherein the step of selectively forming the copper interconnection layer includes the step of metal organic chemical vapor deposition.

16. The method of claim 1, wherein the step of selectively forming the copper interconnection layer includes the step of electroplating.

17. The method of claim 1, wherein the step of forming the second barrier layer on the upper surface and the sides of the copper interconnection layer includes the steps of:

forming a second barrier layer on an upper surface of the copper interconnection layer and on the insulation layer;

forming an etching mask pattern thicker than the copper interconnection layer on a surface of the second barrier layer; and

partially etching and removing the second barrier layer by using the etching mask pattern as a mask.

18. The method of claim 1, wherein the step of selectively forming the seed layer forms a layer having a thickness of 500 Å

or less.

19. The method of claim 14, wherein the step of selectively forming the seed layer forms a layer having a thickness of 500 Å

or less.

20. The method of claim 1, wherein the step of forming grooves in the insulation layer includes the step of wet etching the insulation layer.

21. The method of claim 14, wherein the stop of selectively forming the seed layer includes the step of least one of chemical vapor deposition or sputtering.

22. A method of manufacturing an interconnection layer for a semiconductor device comprising the steps of:

forming a conductive pattern in a surface of a semiconductor substrate or on the surface of the semiconductor substrate;

forming an insulation layer on an upper surface of the conductive pattern;

forming at least one groove having sidewalls and a bottom in the insulation layer exposing upper surfaces of the conductive pattern;

forming a first barrier layer on an upper surface of the insulation layer and on the sidewalls and bottom of the at least one groove;

selectively forming a seed layer directly on and in contact with portions of a surface of the first barrier layer and the sidewalls and the bottom of the at least one groove;

selectively forming a copper interconnection layer on the first barrier layer and the seed layer; and

forming a second barrier layer on the copper interconnection layer.

23. The method of claim 22, wherein the step of forming the second barrier layer on the copper interconnection layer includes the steps of:

forming a second barrier layer on a surface of the copper interconnection layer and on the insulation layer;

forming an etching mask pattern thicker than the copper interconnection layer on a surface of the second barrier layer; and

partially etching and removing the second barrier layer by using the etching mask pattern as a mask.

24. The method of claim 22, wherein the seed layer is deposited by chemical vapor deposition or sputtering.