Electro-magnetic lithographic alignment method

• US 6,294,909 B1
• Filed: 06/07/1995
• Issued: 09/25/2001
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): PATIDAR, JAY M
• Application Number:
  US08/488,380
• Time in Patent Office: 2,302 Days
• Field of Search: 324/226, 324/262, 324/207.11, 324/207.13, 324/207-5-2, 324/207.26, 324/202, 324/207.12
• US Class Current: 324/207.17
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

A method of aligning a lithographic fabrication tool to a substrate to be exposed or patterned by the tool includes the steps of providing a first conductive coil pattern on a surface of the substrate, applying electrical current to the coil pattern, providing a second conductive coil on a surface of the tool, sensing an electro-magnetic field generated by the first coil and the second coil, and aligning the tool according to the signal sensed from the first coil. The method contemplates that electrical current is provided to the first coil from either an external source or the tool. Electrical current is provided by the tool through electrical probes on the tool that contact the first coil, preferably at contact pads. A semiconductor processing lithography apparatus for maskless pattern generation is also disclosed. The apparatus includes a membrane, a conductive coil on a surface of the membrane to sense an electro-magnetic field and generate a signal in accordance with the sensed electro-magnetic field, and a control logic unit mounted on the membrane for controlling the position of the apparatus in accordance with the signal from the conductive coil.

Claims

1. A method of aligning a membrane lithographic fabrication tool comprising a low-stress deposited dielectric layer to a semiconductor substrate to be exposed by the tool, comprising the steps of:

providing a first conductive coil pattern on a surface of the semiconductor substrate;

applying electrical current to the first coil pattern;

providing a second conductive coil on a surface of the tool capable of sensing an electro-magnetic field;

sensing an electro-magnetic field generated by the first coil in the second coil; and

aligning the tool according to the signal sensed by the second coil.

2. The method of claim 1, wherein the tool is provided with a probe point and the electrical current flows through the probe point to the first coil pattern.

3. The method of claim 1, further comprising the step of bringing the surface of the tool near to the surface of the semiconductor substrate to sense the electro-magnetic field generated by the first coil.

4. The method of claim 3, further comprising the step of applying a fluid pressure to bring the tool near the surface of the semiconductor substrate.

5. The method of claim 1, wherein the first coil pattern is coupled to a contact pad and electrical current is applied to the coil pattern through the contact pad.

6. The method of claim 1, wherein aligning comprises aligning to a pattern registration tolerance of less than 25 nm.

7. A semiconductor processing lithography apparatus including closed-loop positioning circuitry, the apparatus comprising:

a membrane comprising a low-stress deposited dielectric layer;

a conductive coil on a surface of the membrane for sensing an electromagnetic field generated by an external source of electromagnetic field and for generating a signal in accordance with the sensed electro-magnetic field; and

a control logic unit mounted on the membrane for controlling the position of the apparatus in accordance with the signal from the conductive coil.

8. The apparatus of claim 7, further comprising an electrode probe point extending from the membrane to contact and supply a signal to the external source and thereby generate an electro-magnetic field at the external source.

9. The apparatus of claim 7, wherein the apparatus is a semiconductor processing lithography apparatus for maskless pattern generation, further comprising a cell array of radiation sources coupled to the surface of the membrane.

10. The apparatus of claim 9, wherein the cell array is one of a Source-Integrated-Light-Valve, a Source-External-Particle-Valve, and a Mechanical-Light-Valve.

11. The apparatus of claim 7 wherein the membrane is made of semiconductor material.

12. The apparatus of claim 7 wherein the membrane is patterned in accordance with a pattern so as to serve as a mask for transferring the pattern to a surface of an integrated circuit.