Method and apparatus for low power differential signaling to reduce power

• US 6,294,933 B1
• Filed: 02/01/2000
• Issued: 09/25/2001
• Est. Priority Date: 02/01/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Muh, Matthew, Chun, Christopher Ky
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TAN, VIBOL
• Application Number:
  US09/495,355
• Time in Patent Office: 602 Days
• Field of Search: 326/30, 326/82, 326/86, 326/90, 327/563, 327/65, 327/69, 327/82
• US Class Current: 326/86
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

A low power differential signaling technique for reducing power in CMOS circuits. An input signal is provided to the input of a transmitter which uses transitions of the input signal to switch between two complementary resistive paths between upper and lower voltages across a common resistive element to develop a differential signal pair. In particular, during a high transition, a first pair of resistive switches are coupled across the common resistor causing current flow in a first direction and, during a low transition of the input signal, a second pair of resistive switches are coupled across the same common resistive element to cause current to flow in the opposite direction. The switching action converts a single-ended input signal to a differential signal pair across the common resistive element. The voltage swing across the differential signal pair is reduced to less than one half of the voltage differential between the upper and lower voltages which represent the source voltages. A receiver converts the differential signal pair back to a single-ended output voltage signal. The conversion of the single-ended input signal to a differential signal pair with a reduced voltage swing provides substantial power savings without the necessity of a voltage reference and further achieves the benefit of increased immunity to common mode noise.

Claims

1. A low power transmitter circuit for converting a single ended input signal to first and second output signals, comprising:

an input terminal for receiving the input signal;

first and second output terminals for transmitting the first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage;

a resistive element connecting the first and second output terminals; and

first and second feed-forward capacitors connected between the input terminal and the first and second output terminals, respectively,

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage.

2. The low power transmitter circuit of claim 1, wherein the first and second feed-forward capacitors include MOS transistor devices.

3. A low power transmitter circuit for converting a single ended input signal to first and second output signals, comprising:

an input terminal for receiving the input signal;

first and second output terminals for transmitting the first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage;

a resistive element connecting the first and second output terminals; and

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage;

wherein the plurality of resistive switches comprise;

a first N-channel MOS transistor having a drain connected to the upper voltage, a gate connected to the input terminal, and a source connected to the first output terminal;

a second P-channel MOS transistor having a drain connected to the lower voltage, a gate connected to the input terminal, and a source connected to the first output terminal;

a third N-channel MOS transistor having a drain connected to the upper voltage, a source connected to the second output terminal, and a gate connected to the input terminal through an inverter; and

a fourth P-channel MOS transistor having a drain connected to the lower voltage, a source connected to the second output terminal, and a gate connected to the input terminal through the inverter.

4. A low power transmitter circuit for converting a single ended input signal to first and second output signals, comprising:

an input terminal for receiving the input signal;

first and second output terminals for transmitting the first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage; and

a resistive element connecting the first and second output terminals;

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage;

wherein the resistive element comprises;

a MOS transistor having a drain connected to the first output terminal, a gate connected to a selected one of the upper voltage and the lower voltage, and a source connected to the second output terminal.

5. A clock circuit, comprising:

a transmitter comprising;

an input terminal for receiving an input clock signal;

first and second output terminals for transmitting first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage; and

a resistive element connecting the first and second output terminals;

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage; and

a receiver circuit for converting the first and second output signals to a single ended output clock signal and

first and second feed-forward capacitors connected between the input terminal and the first and second output terminals, respectively.

6. The clock circuit of claim 5, wherein the first and second feed-forward capacitors include MOS transistor devices.

7. A low power transmitter circuit for converting a single ended input signal to first and second output signals, comprising:

an input terminal for receiving the input signal;

first and second output terminals for transmitting the first and second output signals having first and second voltage levels, respectively;

a first N-channel MOS transistor having a drain connected to an upper voltage, a gate connected to the input terminal, and a source connected to the first output terminal;

a second P-channel MOS transistor having a drain connected to a lower voltage, a gate connected to the input terminal, and a source connected to the first output terminal;

an inverter connected to the input terminal an having an inverter output;

a third N-channel MOS transistor having a drain connected to the upper voltage, a gate connected to the inverter output, and a source connected to the second output terminal;

a fourth P-channel MOS transistor having a drain connected to the lower voltage, a gate connected to the inverter output, and a source connected to the second output terminal;

a fifth MOS transistor having a drain connected to the first output terminal, a gate connected to a selected one of the upper voltage and the lower voltage, and a source connected to the second output terminal; and

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage.

8. The low power transmitter circuit of claim 7, wherein the first and second output signals are differential.

9. The low power transmitter circuit of claim 7, further comprising:

first and second feed-forward capacitors connected between the input terminal and the first and second output terminals, respectively.

10. The low power transmitter circuit of claim 7, wherein the transmitter circuit is internal to an integrated circuit chip.

11. An integrated circuit chip having a low power transmitter circuit for converting a single ended input signal to first and second output signals, the transmitter circuit comprising:

an input terminal for receiving the input signal;

first and second output terminals for transmitting the first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage;

a resistive element connecting the first and second output terminals; and

first and second feed-forward capacitors connected between the input terminal and the first and second output terminals, respectively;

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage.

12. A method for reducing power consumption in a digital circuit, comprising:

applying an input signal to the circuit;

providing an upper voltage and a lower voltage;

using a transition of the input signal to switch between two complementary resistive paths between the upper voltage and the lower voltage across a common resistive element to develop a differential signal pair having first and second voltage levels; and

reducing voltage swing between the first and second voltage levels to less than one half of a difference between the upper voltage and the lower voltage;

wherein the step of increasing the speed of the differential signal pair comprises;

connecting first and second feed-forward capacitors between the input signal and the differential signal pair.

13. A clock circuit, comprising:

a transmitter circuit comprising;

an input terminal for receiving an input clock signal;

first and second output terminals for transmitting first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage; and

a resistive element connecting the first and second output terminals;

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage; and

a receiver circuit for converting the first and second output signals to a single ended output clock signal,

wherein the plurality of resistive switches comprise;

a first N-channel MOS transistor having a drain connected to the upper voltage, a gate connected to the input terminal, and a source connected to the first output terminal;

a second P-channel MOS transistor having a drain connected to the lower voltage, a gate connected to the input terminal, and a source connected to the first output terminal;

third N-channel MOS transistor having a drain connected to the upper voltage, a source connected to the second output terminal, and a gate connected to the input terminal through an inverter; and

a fourth P-channel MOS transistor having a drain connected to the lower voltage, a source connected to the second output terminal, and a gate connected to the input terminal through the inverter.

14. clock circuit, comprising:

a transmitter circuit comprising;

an input terminal for receiving an input clock signal;

first and second output terminals for transmitting first and second output signals having first and second voltage levels, respectively;

a plurality of resistive switches connected to the input terminal and the first and second output terminals, the plurality of resistive switches further connected to an upper voltage and a lower voltage; and

a resistive element connecting the first and second output terminals;

wherein a difference between the first and second voltage levels is less than one half of a difference between the upper voltage and the lower voltage; and

a receiver circuit for converting the first and second output signals to a single ended output clock signal;

wherein the resistive element comprises;

a MOS transistor having a drain connected to the first output terminal, a gate connected to a selected one of the upper voltage and the lower voltage, and a source connected to the second output terminal.