Method and apparatus for self correcting parallel I/O circuitry

• US 6,294,937 B1
• Filed: 05/25/1999
• Issued: 09/25/2001
• Est. Priority Date: 05/25/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Steele, David P., Crafts, Harold S.
• Primary Examiner(s): TON, MY TRANG
• Application Number:
  US09/322,329
• Time in Patent Office: 854 Days
• Field of Search: 327/147, 327/149, 327/150, 327/153, 327/156, 327/158, 327/161, 327/261, 327/276, 327/277, 327/297, 327/284, 327/292, 375/376
• US Class Current: 327/158
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.

Claims

1. A variable delay circuit for delaying bus signal timing comprising:

a phase locked loop, wherein the phase locked loop generates a control signal; and

a variable delay element connected to a bus line for delaying a signal on the bus line and further connected to the phase lock loop, wherein the control signal from the phase locked loop controls the variable delay element and stabilizes bus signal timing delays.

2. A variable delay circuit as recited in claim 1, wherein the variable delay element comprises at least one delay unit, the delay circuit further comprising:

a delay unit control signal generator, the delay unit control signal generator is connected to the variable delay element, wherein the delay unit control signal generator generates a delay unit signal for turning off at least one delay unit.

3. A variable delay circuit as recited in claim 2, wherein an initial timing delay value of the delay unit signal is stored in memory.

4. A variable delay circuit as recited in claim 3, wherein the memory stores a timing delay value related to signal timing.

5. A variable delay circuit as recited in claim 4, wherein the memory stores the timing delay value related to bus skew.

6. A variable delay circuit as recited in claim 2, wherein the phase locked loop comprises at least one delay.

7. A variable delay circuit for delaying bus signal timing comprising:

a memory for storing a value related to an initial number of active delay units;

a logic element for selecting at least one of a plurality of delay units to activate, the logic element being connected to the memory, wherein the value related to an initial number of active delay units is used by the logic element to select at least one of the plurality of delay units to activate; and

a bus carrying a data signal connected to a variable delay element containing the plurality of delay units, wherein the active units delay the signal timing of the bus.

8. A variable delay circuit for delaying bus signal timing as recited in claim 7, further comprising:

a phase locked loop circuit connected to the variable delay element, wherein the phase locked loop generates a control signal which is at least partially dependent on temperature and which controls the delay units within the variable delay element.

9. A variable delay circuit for delaying bus signal timing as recited in claim 8, wherein the memory, the variable delay element comprising a plurality of delay units, and the phase locked loop all reside on a chip.

10. A variable delay circuit for delaying bus signal timing on a plurality of bus lines comprising:

connect to each bus line, a variable delay circuit comprising

a plurality of delay units;

a logic element for selecting at least one of the plurality of delay units to activate; and

a memory for storing a value, wherein the value is used by the logic element for adjusting bus signal timing delay within operational limits of the bus by activating at least one logic element.

11. A variable delay circuit recited in claim 10, wherein the delay of the bus signal timing is regulated by a phase locked loop control signal.

12. A method for delaying bus signal timing using a variable delay circuit, the method comprising:

generating a stabilization signal in a phase locked loop;

generating a control signal;

stabilizing bus signal timing delays from a variable delay element connected to a bus line for delaying a signal on the bus line using the stabilization signal, and

controlling bus signal timing delays from a variable delay element connected to the bus line for delaying a signal on the bus line using the control signal.

13. The method for delaying bus signal timing as recited in claim 12, wherein the variable delay element comprises at least one delay unit, the method further comprising:

feeding the control signal to a delay unit control signal generator, the delay unit control signal generator being connected to the variable delay element; and

generating a delay unit signal using the delay unit control signal generator for turning off at least one delay unit.

14. The method for delaying bus signal timing as recited in claim 13, further comprising:

retrieving an initial value of the delay unit signal that is stored in a memory.

15. The method for delaying bus signal timing as recited in claim 14, wherein the memory stores a timing delay value related to signal timing.

16. The method for delaying bus signal timing as recited in claim 15, wherein the memory stores a timing delay value related to bus skew.

17. The method for delaying bus signal timing as recited in claim 12, wherein the phase locked loop comprises at least one delay.

18. A method for delaying bus signal timing using a variable delay circuit, the method comprising:

storing a value related to an initial number of active delay elements in a memory; and

selecting at least one of the plurality of delay units to activate using a logic element, wherein the value related to a initial number of active delay units is used by the logic element to activate at least one of the plurality of delay units.

19. The method for delaying bus signal timing using a variable delay circuit as recited in claim 18, wherein a phase locked loop circuit is connected to a variable delay unit, the method further comprising:

generating a control signal by a phase locked loop circuit, wherein the control signal is at least partially dependent on temperature; and

regulating bus signal timing delay using the control signal.

20. The method for delaying bus signal timing using a variable delay circuit as recited in claim 19, wherein the memory, the variable delay element comprising a plurality of delay units, and the phase locked loop all reside on a chip.

21. A method for delaying bus signal timing using a variable delay circuit, the method comprising:

connecting to each bus line a variable delay circuit;

for each bus line;

delaying a signal using a plurality of delay units;

selecting at least one of the plurality of delay units to activate using a logic element;

reading a value from memory; and

activating at least one delay element using the value, wherein the value is used by the logic element for adjusting bus signal timing delay within operational limits of the bus.

22. The method for delaying bus signal timing using variable delay circuits as recited in claim 21 further comprises:

regulating the delay of the bus signal timing using a phase locked loop control signal.