Phase lock loop circuit using signal estimator

• US 6,294,960 B1
• Filed: 12/03/1999
• Issued: 09/25/2001
• Est. Priority Date: 12/04/1998
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Omori, Youko
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/454,403
• Time in Patent Office: 662 Days
• Field of Search: 331/14, 331/25, 455/296
• US Class Current: 331/14
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se

Abstract

A signal estimator estimates a transmission signal series using Viterbi algorithm, and outputs an estimated signal and a minimum path metric signal. A switching unit is controlled by a control signal in such a manner that, for a certain period from the start of the operation of PLL which requires quick response, a minimum path metric history signal is selected, while, in the other case, an estimated signal is selected. A replica generator generates a replica signal using a signal output from the switching unit. The generation of the replica signal using the path metric history signal offers quick response, but on the other hand, the accuracy is low. On the other hand, the use of the estimated signal offers high accuracy, but on the other hand, the response speed is low. Thus, a phase change contained in a received signal is corrected in a highly accurate and quick manner.

Claims

1. A phase lock loop circuit using a signal estimator, for detecting and correcting a phase shift contained in a received signal and, in addition, removing transmission path distortion, said phase lock loop comprising:

a signal estimator for estimating a transmission signal series using a Viterbi algorithm from the received signal and outputting the transmission signal series as an estimated signal and, in addition, outputting a minimum path metric history signal obtained as a result of temporary estimation of the signal from the current path status without traceback in the Viterbi algorithm;

switching means which, when a control signal is active, selectively outputs the estimated signal, and, when the control signal is inactive, selectively outputs the minimum path metric history signal;

replica generating means for generating a replica signal using a signal selected by the switching means;

feedback loop means for detecting a phase difference contained in the received signal from the replica signal and the received signal to correct the phase difference; and

control signal generating means for rendering the control signal inactive only for a predetermined certain period from the start of the operation of the feedback loop means.

2. The phase lock loop circuit using a signal estimator according to claim 1, wherein the control signal generating means comprises:

a counter for counting the time elapsed from the start of the operation of the feedback loop means;

means which, when the value of the counter is smaller than the predetermined certain value, renders the control signal inactive, and, as soon as the value of the counter becomes not less than the predetermined certain value, renders the control signal active.

5. The phase lock loop circuit using a signal estimator according to claim 1, wherein the feedback loop means comprises:

a phase detector for detecting the phase difference between the replica signal and the received signal;

a filter for filtering the phase difference detected by the phase detector to output the bandwidth-limited signal;

a voltage-controlled oscillator for generating and outputting a signal of which the frequency is controlled by the signal output from the filter; and

a phase rotator for rotating the phase of the received signal based on the signal generated by the voltage-controlled oscillator to correct the phase shift contained in the received signal.

6. The phase lock loop circuit using a signal estimator according to claim 5, further comprising delay time switching means which, when the control signal is inactive, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates a minimum path metric history signal which is then used in the replica generator to generate a replica signal, and, when the control signal is active, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates an estimated signal which is then used in the replica generator to generate a replica signal.

7. The phase lock loop circuit using a signal estimator according to claim 2, wherein the feedback loop means comprises:

a phase detector for detecting the phase difference between the replica signal and the received signal;

a filter for filtering the phase difference detected by the phase detector to output the bandwidth limited signal;

a voltage-controlled oscillator for generating and outputting a signal of which the frequency is controlled by the signal output from the filter; and

a phase rotator for rotating the phase of the received signal based on the signal generated by the voltage-controlled oscillator to correct the phase shift contained in the received signal.

10. The phase lock loop circuit using a signal estimator according to claim 7, further comprising delay time switching means which, when the control signal is inactive, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates a minimum path metric history signal which is then used in the replica generator to generate a replica signal, and, when the control signal is active, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates an estimated signal which is then used in the replica generator to generate a replica signal.

3. A phase lock loop circuit using a signal estimator, for detecting and correcting a phase shift contained in a received signal and, in addition, removing transmission path distortion, said phase lock loop comprising:

a signal estimator for estimating a transmission signal series using a Viterbi algorithm from the received signal and outputting the transmission signal series as an estimated signal and, in addition, outputting a minimum path metric history signal obtained as a result of temporary estimation of the signal from the current path status without traceback in the Viterbi algorithm;

switching means which, when a control signal is active, selectively outputs the estimated signal, and, when the control signal is inactive, selectively outputs the minimum path metric history signal;

replica generating means for generating a replica signal using a signal selected by the switching means;

feedback loop means for detecting a phase difference contained in the received signal from the replica signal and the received signal to correct the phase difference; and

control signal generating means which renders the control signal inactive when the feedback loop means is in a predetermined certain period from the start of the operation of the feedback loop means or when the phase difference detected in the feedback loop means is not less than a predetermined certain value.

4. The phase lock loop circuit using a signal estimator according to claim 3, wherein the control signal generating means comprises:

a counter for counting the time elapsed from the start of the operation of the feedback loop means;

means for deciding whether or not the value of the counter is not less than the predetermined certain value;

means for deciding whether or not the absolute value of the phase difference between the replica signal and the received signal detected by the feedback means is not less than the predetermined certain value; and

logical operation means which, only when the value of the counter is not less than the predetermined certain value and, at the same time, the absolute value of the phase difference is smaller than the predetermined certain value, renders the control signal active, and, in the other case, renders the control signal inactive.

8. The phase lock loop circuit using a signal estimator according to claim 3, wherein the feedback loop means comprises:

a phase detector for detecting the phase difference between the replica signal and the received signal;

a filter for filtering the phase difference detected by the phase detector to output the bandwidth limited signal;

a voltage-controlled oscillator for generating and outputting a signal of which the frequency is controlled by the signal output from the filter; and

a phase rotator for rotating the phase of the received signal based on the signal generated by the voltage-controlled oscillator to correct the phase shift contained in the received signal.

9. The phase lock loop circuit using a signal estimator according to claim 4, wherein the feedback loop means comprises:

a phase detector for detecting the phase difference between the replica signal and the received signal;

a filter for filtering the phase difference detected by the phase detector to output the bandwidth limited signal;

a voltage-controlled oscillator for generating and outputting a signal of which the frequency is controlled by the signal output from the filter; and

a phase rotator for rotating the phase of the received signal based on the signal generated by the voltage-controlled oscillator to correct the phase shift contained in the received signal.

11. The phase lock loop circuit using a signal estimator according to claim 8, further comprising delay time switching means which, when the control signal is inactive, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates a minimum path metric history signal which is then used in the replica generator to generate a replica signal, and, when the control signal is active, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates an estimated signal which is then used in the replica generator to generate a replica signal.

12. The phase lock loop circuit using a signal estimator according to claim 9, further comprising delay time switching means which, when the control signal is inactive, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates a minimum path metric history signal which is then used in the replica generator to generate a replica signal, and, when the control signal is active, outputs the received signal output from the phase rotator after delay by a time corresponding to the delay time elapsed until, after the input of the received signal output from the phase rotator into the signal estimator, the signal estimator generates an estimated signal which is then used in the replica generator to generate a replica signal.