8B/10B encoder system and method

• US 6,295,010 B1
• Filed: 07/01/1999
• Issued: 09/25/2001
• Est. Priority Date: 07/02/1998
• Status: Expired due to Term

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Thiesfeld, Charles W.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/345,913
• Time in Patent Office: 817 Days
• Field of Search: 341/58, 341/59
• US Class Current: 341/58
• CPC Class Codes: H03M 7/14 Conversion to or from non-weighted codes
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

According to one embodiment of the present invention a number of input bits are received in a first encoder circuit and the input bits are encoded to generate encoded bits in the first encoder circuit. An input disparity bit is generated from the encoded bits, and the input bits and the input disparity bit are received in a second encoder circuit. The input bits are then encoded into a number of output bits based on the input disparity bit in the second encoder circuit. According to another embodiment of the present invention an encoder system includes a first encoder circuit having a number of inputs coupled to receive a number of input signals, to encode the input signals, and to generate a disparity signal at an output based on the encoded input signals. The encoder system also includes a second encoder circuit having a number of inputs coupled to receive the input signals and the disparity signal to encode the input signals into a number of output signals at a number of outputs based on the disparity signal.

Claims

1. A method of encoding comprising steps of:

(a) receiving a plurality of input bits in a first encoder circuit;

(b) encoding the input bits to generate encoded bits in the first encoder circuit;

(c) generating an input disparity bit from the encoded bits;

(d) receiving the input bits and the input disparity bit in a second encoder circuit; and

(e) encoding the input bits into a plurality of output bits based on the input disparity bit in the second encoder circuit.

2. The method of claim 1 wherein generating step (c) comprises steps of:

(c)(i) encoding the input bits to generate the encoded bits and an output disparity bit based on a disparity of the encoded bits in the first encoder circuit; and

(c)(ii) generating the input disparity bit from the output disparity bit.

3. The method of claim 1 wherein generating step (c) comprises steps of:

(c)(i) generating an input disparity bit to be equal to a preceding input disparity bit if the encoded bits have a neutral disparity; and

(c)(ii) generating the input disparity bit to be different from the preceding input disparity bit if the encoded bits have a positive or a negative disparity.

4. The method of claim 1 wherein:

receiving step (a) comprises receiving a plurality of input bits in a plurality of first encoder circuits in a first clock cycle;

encoding step (b) comprises encoding the input bits to generate encoded bits in the first encoder circuits in the first clock cycle;

generating step (c) comprises generating a plurality of output disparity bits based on a disparity of the encoded bits and generating a plurality of input disparity bits from the output disparity bits in the first clock cycle;

receiving step (d) comprises receiving the input bits and the input disparity bits in a plurality of second encoder circuits in a second clock cycle following the first clock cycle; and

encoding step (e) comprises encoding the input bits into a plurality of output bits having a disparity determined by the input disparity bits in the second encoder circuits in the second clock cycle.

5. The method of claim 1, further comprising storing a disparity bit to be used to encode a subsequent plurality of input bits into a plurality of output bits.

6. The method of claim 1 wherein:

receiving step (a) comprises receiving a plurality of input bytes in a plurality of first 8B/10B encoder circuits in a first clock cycle, wherein an 8B/10B encoder circuit is defined as an encoder circuit to encode a byte having 8 bits into a transmission character having 10 bits according to a transmission code;

encoding step (b) comprises encoding the input bytes to generate a plurality of transmission characters in the first 8B/10B encoder circuits in the first clock cycle;

generating step (c) comprises generating a plurality of output disparity bits based on a disparity of the transmission characters and generating a plurality of input disparity bits from the output disparity bits in the first clock cycle;

receiving step (d) comprises receiving the input bytes and the input disparity bits in a plurality of second 8B/10B encoder circuits in a second clock cycle following the first clock cycle; and

encoding step (e) comprises encoding the input bytes into a plurality of transmission characters having a disparity determined by the input disparity bits in the second 8B/10B encoder circuits in the second clock cycle.

7. The method of claim 6 wherein generating step (c) comprises steps of:

(c)(i) generating an output disparity bit for each transmission character indicating a disparity of the transmission character; and

(c)(ii) generating an input disparity bit for each output disparity bit, the input disparity bit being the same as a preceding input disparity bit if the disparity of the corresponding transmission character is neutral and the input disparity bit being different from the preceding input disparity bit if the disparity of the corresponding transmission character is positive or negative.

8. The method of claim 6, further comprising storing one of the input disparity bits generated in the first clock cycle to be used to send to the second 8B/10B encoder circuits to encode a subsequent plurality of input bytes in a third clock cycle following the second clock cycle.

9. An encoder system comprising:

a first encoder circuit having a plurality of inputs coupled to receive a plurality of input signals, to encode the input signals into encoded input signals, and to generate a disparity signal at an output based on the encoded input signals; and

a second encoder circuit having a plurality of inputs coupled to receive the input signals and the disparity signal to encode the input signals into a plurality of output signals at a plurality of outputs based on the disparity signal.

10. The encoder system of claim 9 wherein:

the first encoder circuit comprises one or more first encoder circuits each having input pins coupled to receive input bits, a clock input, and an output pin to generate an output disparity bit; and

the second encoder circuit comprises one or more second encoder circuits each having input pins coupled to receive the input bits, a clock input, an input to receive an input disparity bit from the first encoder circuits, and output pins to generate encoded output bits based on the input bits and the input disparity bit.

11. The encoder system of claim 10, further comprising:

an exclusive-OR gate for each first encoder circuit, each exclusive-OR gate having a first input coupled to the output pin of a corresponding first encoder circuit to receive the output disparity bit and a second input coupled to receive a preceding input disparity bit, the exclusive-OR gate having an output to generate a subsequent input disparity bit;

a current storage element for each exclusive-OR gate, each current storage element to store the subsequent input disparity bit and to relay the input disparity bit to a respective one of the second encoder circuits in a subsequent clock cycle; and

a carryover storage element to store the subsequent input disparity bit of one of the first encoder circuits to a subsequent clock cycle.

12. The encoder system of claim 11 wherein the current storage elements and the carryover storage element each comprise a D flip-flop.

13. The encoder system of claim 9 wherein:

the first encoder circuit comprises two first 8B/10B encoder circuits each having input pins coupled to receive input bits, a clock input, an output pin to generate an output disparity bit, wherein an 8B/10B encoder circuit is defined as an encoder circuit to encode a byte having 8 bits into a transmission character having 10 bits according to a transmission code; and

the second encoder circuit comprises two second 8B/10B encoder circuits each having input pins coupled to receive the input bits, a clock input, an input to receive an input disparity bit from the first 8B/10B encoder circuits, and outputs to generate encoded output bits based on the input bits and the input disparity bit.

14. A port of the type including the encoder system of claim 9 and further comprising:

a deserializer coupled to receive signals from an interface;

a decoder coupled to receive deserialized signals from the deserializer and to generate decoded signals;

a first-in, first-out buffer coupled between the decoder and the encoder system to store the decoded signals and to provide the decoded signals to the encoder system; and

a serializer coupled to receive the output signals from the encoder system, to serialize the output signals, and to transmit the output signals to the interface.

15. A disc drive of the type including the port of claim 14 and further comprising:

a base;

a disc rotatably attached to the base;

a spindle motor attached to the base and coupled to rotate the disc;

an actuator attached to the base, one end of the actuator having a transducer and another end of the actuator having a voice coil which forms a portion of a voice coil motor; and

a circuit coupled to the transducer to exchange signals with the transducer to read data from and write data to the disc, the circuit including the port coupled to the interface.

16. An information handling system of the type including the disc drive of claim 15 and further comprising:

a central processing unit operatively coupled to the disc drive;

a data storage device operatively coupled to the central processing unit; and

an input/output subsystem operatively coupled to the central processing unit.

17. An information handling system comprising:

a central processing unit operatively coupled to an interface;

a data storage device operatively coupled to the interface;

an input/output subsystem operatively coupled to the interface; and

a disc drive operatively coupled to the interface through a port, the port comprising an encoder system, the encoder system comprising;

a first encoder circuit having a plurality of inputs coupled to receive a plurality of input signals, to encode the input signals into encoded input signals, and to generate a disparity signal at an output based on the encoded input signals; and

a second encoder circuit having a plurality of inputs coupled to receive the input signals and the disparity signal to encode the input signals into a plurality of output signals at a plurality of outputs based on the disparity signal.

18. The information handling system of claim 17 wherein:

the first encoder circuit comprises one or more first 8B/10B encoder circuits each having input pins coupled to receive input bits, a clock input, and an output pin to generate an output disparity bit, wherein an 8B/10B encoder circuit is defined as an encoder circuit to encode a byte having 8 bits into a transmission character having 10 bits according to a transmission code; and

the second encoder circuit comprises one or more second 8B/10B encoder circuits each having input pins coupled to receive the input bits, a clock input, an input to receive an input disparity bit from the first 8B/10B encoder circuits, and output pins to generate encoded output bits based on the input bits and the input disparity bit.

19. The information handling system of claim 17 wherein the port further comprises:

a deserializer coupled to receive signals from the interface;

a decoder coupled to receive deserialized signals from the deserializer and to generate decoded signals;

a first-in, first-out buffer coupled between the decoder and the encoder system to store the decoded signals and to provide the decoded signals to the encoder system; and

a serializer coupled to receive the output signals from the encoder system, to serialize the output signals, and to transmit the output signals to the interface.