Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images

• US 6,295,054 B1
• Filed: 07/21/1998
• Issued: 09/25/2001
• Est. Priority Date: 07/20/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: McKnight, Douglas J.
• Primary Examiner(s): CHANG, KENT WU
• Application Number:
  US09/119,975
• Time in Patent Office: 1,162 Days
• Field of Search: 345/84, 345/87, 345/89, 345/90, 345/98, 345/99, 345/55, 345/205, 345/213, 345/148, 345/186, 345/508, 345/518
• US Class Current: 345/205
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2320/0633 by amplitude modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2033 : with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/2037 : with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/3406 : Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3648 : using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 : the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A device such as a display device or a spatial light modulator can store pixel data in a plurality of small circuits coupled to pixel mirrors and simultaneously drive these pixel mirrors a frame at a time. This device is particularly beneficial for implementing improved image quality techniques which can convert binary images to grey-scale images and/or separate red, green and blue images into color images and displaying those images using the natural process of integration which occurs when a person views images at sufficiently high rates.

Claims

1. A device, comprising:

a pixel electrode;

a driving circuit coupled to said pixel electrode for switching a data signal to said pixel electrode at a present pixel value; and

a holding unit contained within said driving circuit for holding a future pixel value while said pixel electrode is at said present pixel value.

2. The device of claim 1, wherein said holding unit comprises a transistor.

3. The device of claim 2, wherein said driving circuit comprises said transistor.

4. The device as claimed in claim 3, wherein said present pixel value and said future pixel value are analog pixel values.

5. The device of claim 1, wherein said driving circuit comprises a first line for receiving a frame buffering signal indicating when said driving circuit receives said future pixel value.

6. The device of claim 5, wherein said present pixel value and said future pixel value are analog pixel values.

7. The device of claim 1, wherein said holding unit comprises two single pixel value holding units for holding two future pixel values for future display.

8. The device of claim 7, wherein said two pixel value holding units comprise a first pixel value holding unit for holding a first future pixel value and a second pixel value holding unit for holding a second future pixel value, wherein the first future pixel value is displayed followed by the second future pixel value.

9. The device of claim 1, wherein said driving circuit includes a first line for receiving frame buffering signals indicating when said driving circuit receives the future pixel value.

10. The device of claim 9, wherein said holding unit comprises three single pixel value holding units for holding three pixel values for future display.

11. The device of claim 10, wherein said three single pixel value holding units hold first, second, and third future pixel values, respectively, wherein the first future pixel value is displayed followed by the second future pixel value, which in turn is followed by the third future pixel value.

12. The device of claim 11, wherein said driving circuit includes a first line for receiving frame buffering signals indicating when said driving circuit receives the first future pixel value, the second future pixel value and the third future pixel value.

24. The device of claim 1, further comprising a signal scanner coupled to said holding unit, said signal scanner outputting said present pixel value followed by said future pixel value to said holding unit.

25. The device of claim 8, further comprising a signal scanner coupled to said two single pixel value holding units, said signal scanner outputting said first future pixel value to one of said two single pixel value holding units and outputting said second future pixel value to the other of said two single pixel value holding units.

26. The device of claim 25, wherein said two single pixel value holding units comprise two transistors.

27. The device of claim 6, wherein said two single pixel value holding units comprise three transistors.

28. The device of claim 10, wherein said three single pixel value holding units comprise three transistors.

59. The device of claim 1, wherein the driving circuit comprises:

a first transistor having a first electrode connected to selectively receive a first prescribed voltage, a control electrode connected to receive the pixel values and a second electrode connected to the pixel electrode at a connection point; and

a reset circuit connected to the connection point.

60. The device of claim 1, wherein the driving circuit comprises:

a first transistor having a first electrode connected to selectively receive a first prescribed voltage and a second electrode connected to the pixel electrode at a connection point;

a second transistor having a first electrode connected to selectively receive the first prescribed voltage and a second electrode connected to the connection point;

a third transistor having a first electrode connected to selectively receive the first prescribed voltage and a second electrode connected to the connection point; and

a reset circuit connected to the connection point.

61. The device of claim 60, wherein the holding unit includes the first, second and third transistors, wherein the holding unit is adapted to hold three future pixel values, and wherein the future pixel values are at least one of first, second and third colors.

13. A pixel buffer array, compromising:

a plurality of pixel electrodes;

a plurality of driving circuits respectively coupled to said plurality of pixel electrodes for driving said plurality of pixel electrodes to a respective plurality of present pixel values;

a plurality of holding units respectively contained within said plurality of driving circuits for holding a respective plurality of future pixel values while said plurality of driving circuits respectively drives said plurality of pixel electrodes with the respective plurality of present pixel values, wherein each of the driving circuits is for switching the pixel values to a corresponding pixel electrode of the pixel electrodes.

14. The pixel buffer array of claim 13, wherein said plurality of holding units comprise a respective plurality of transistors.

15. The pixel buffer array of claim 14, wherein said respective plurality of driving circuits comprise said plurality of transistors.

16. The pixel buffer array of claim 13, wherein said plurality of present and future pixel values are analog pixel values.

17. The pixel buffer array of claim 13, wherein said plurality of driving circuits include a first line for receiving a frame buffering signal indicating when said plurality of pixel electrodes receive the respective plurality of future pixel values.

18. The pixel buffer array of claim 17, wherein said plurality of driving circuits include a first line for receiving a frame buffering signal indicating when said plurality of pixel electrodes approximately simultaneously receive the respective plurality of future pixel values.

19. The pixel buffer array of claim 13, wherein each said plurality of holding units comprises two single pixel value holding units for holding two pixel values for future display.

20. The pixel buffer array of claim 13, wherein each of said plurality of holding units comprises two single pixel value holding units for holding a respective first future pixel value corresponding to a first future frame and for holding a respective second future pixel value corresponding to second future frame, wherein the first future frame is approximately simultaneously displayed and then said second future frame is approximately simultaneously displayed.

21. The pixel buffer array of claim 13, wherein said plurality of driving circuits are coupled to a first line for receiving frame buffering signals indicating when said plurality of driving circuits receive the plurality of first future pixel values followed by the plurality of second future pixel values.

22. The pixel buffer array of claim 13, wherein each of said holding units comprises three single pixel value holding units for holding three pixel values for future display.

23. The pixel buffer array of claim 22, wherein each of said plurality of holding units comprises three single pixel value holding units for holding a respective first future pixel value corresponding to a first future frame, a respective second future pixel value corresponding to a second future frame, and a respective third future pixel value corresponding to a third future frame, wherein the first future frame is approximately simultaneously displayed followed by the second future frame and then the third future frame.

29. A device for driving a pixel, comprising:

a driving circuit for driving said pixel at a present pixel value, wherein the driving circuit comprises,

a first transistor having a first electrode connected to a first prescribed voltage;

a second transistor having a first electrode connected to a second electrode of the first transistor; and

a third transistor having a first electrode connected at a connection point to a second electrode of the second transistor and the pixel, wherein a second electrode of the third transistor is connected to a second prescribed voltage; and

a holding unit contained within said driving circuit for receiving and holding at least one future pixel value while said pixel is at said present pixel value.

30. The device of claim 29, wherein said holding unit comprises a transistor.

31. The device of claim 29, wherein said driving circuit comprises a transistor.

32. The device of claim 29, wherein said present and future pixel values are analog pixel values.

33. The device of claim 29, wherein said holding unit is adapted to concurrently hold a plurality of future pixel values.

34. The device of claim 33, wherein said holding unit is adapted to concurrently hold two future pixel values.

35. The device of claim 33, wherein said holding unit is adapted to concurrently hold three future pixel values.

36. The device of claim 35, wherein said holding unit is adapted to concurrently hold red, green and blue future pixel values.

37. The device of claim 29, further comprising a resetting circuit for resetting said pixel while said holding unit is receiving at least one future pixel value.

62. The device of claim 29, wherein a control electrode of the second transistor receives the pixel values through a selector controlled by a first control signal, and wherein the second transistor is the holding unit.

63. The device of claim 62, wherein control electrodes of the first and third transistors receive second and third control signals, respectively, and wherein the selector includes a transistor having a first electrode coupled to a first signal line, a second electrode coupled to the control electrode of the second transistor and a control electrode coupled to a second signal line.

64. The device of claim 63, wherein the first signal line is a data line, the second signal line is a gate line, the second control signal is a pull-up signal and the third control signal is a pull-down signal.

65. The device of claim 63, wherein the first to third transistors are n-channel transistors, the first prescribed voltage is a pull-up voltage and the second prescribed voltage is a ground voltage.

66. The device of claim 29, wherein the driving circuit comprises:

a fourth transistor having a first electrode connected to the first prescribed voltage; and

a fifth transistor having a first electrode connected to a second electrode of the fourth transistor, and a second electrode connected to the connection point, and wherein a control electrode of the fifth transistor receives the pixel values through a selector controlled by a fourth control signal.

67. The device of claim 66, wherein control electrodes of the first, third and fourth transistors receive second, third and fifth control signals, respectively, wherein the selector includes a transistor having a first electrode coupled to a first signal line, a second electrode coupled to the control electrode of the fifth transistor and a control electrode coupled to a second signal line, and wherein the holding unit includes the second and fifth transistors.

68. The device of claim 29, further comprising:

fourth and sixth transistors having a first electrode connected to the first prescribed voltage; and

fifth and seventh transistors, each having a first electrode respectively connected to a second electrode of the fourth and sixth transistors, wherein second electrodes of the fifth and seventh transistors are connected to the connection point, and wherein control electrodes of the second, fifth and seventh transistors receive the pixel values through a selector, and wherein the holding unit includes the second, fifth and seventh transistors, and wherein the holding unit is adapted to concurrently hold three future pixel values.

38. A method of driving a pixel, comprising:

driving a pixel at a present pixel value using a pixel driving circuit, wherein the pixel driving circuit switches a data signal to the pixel; and

receiving and holding at least one future pixel value at a holding unit contained within said driving circuit while said pixel is at said present pixel value.

39. The method of claim 38, wherein said future pixel value is received and held at a transistor.

40. The method of claim 38, wherein said pixel is driven with said present pixel value using a transistor.

41. The method of claim 38, wherein said present and future pixel values are analog pixel values.

42. The method of claim 38, wherein receiving and holding at least one future pixel value at a holding unit comprises receiving a plurality of future pixel values and concurrently holding said plurality of future pixel values at said holding unit.

43. The method of claim 42, wherein concurrently holding said plurality of future pixel values comprises holding two future pixel values.

44. The method of claim 42, wherein concurrently holding said plurality of future pixel values comprises holding three future pixel values.

45. The method of claim 44, wherein concurrently holding three future pixel values comprises concurrently holding red, green and blue future pixel values.

46. A method of driving a pixel, comprising:

driving a pixel at a present pixel value using a pixel driving circuit that includes a driving unit consisting of a single element;

receiving and holding at least one future pixel value at a holding unit contained within said driving unit while said pixel is at said present pixel value; and

resetting said pixel while said holding unit is receiving said at least one future pixel value.

47. The method of 46, wherein resetting said pixel comprises setting said pixel to substantially zero volts.

48. The method of 46, wherein receiving and holding at least one future pixel value at a holding unit comprises receiving a plurality of future pixel values and concurrently holding said plurality of future pixel values at said holding unit in a corresponding one of a plurality of driving units each consisting of a single element, wherein said plurality of future pixel values are at least one of first, second and third colors.

49. The method of claim 48, wherein concurrently holding said plurality of future pixel values comprises holding two future pixel values.

50. The method of claim 48, wherein concurrently holding said plurality of future pixel values comprises holding three future pixel values.

51. The method of claim 50, wherein concurrently holding three future pixel values comprises concurrently holding red, green and blue future pixel values.

52. A method of driving a pixel, comprising:

driving a pixel at a present pixel value using a pixel driving circuit coupled to said pixel for switching a data signal to said pixel; and

independently holding at least one future pixel value at a holding unit contained within said driving circuit while said pixel is at said present pixel value.

53. The method of claim 52, further comprising resetting said pixel while said holding unit is independently holding said at least one future pixel value.

54. The method of claim 53, wherein resetting said pixel comprises setting said pixel to substantially zero volts.

55. The method of claim 52, wherein independently holding at least one future pixel value at a holding unit comprises concurrently holding a plurality of future pixel values at said holding unit, wherein the plurality of future pixel values are at least one of first, second and third colors.

56. The method of claim 55, wherein concurrently holding said plurality of future pixel values comprises holding two future pixel values.

57. The method of claim 55, wherein concurrently holding said plurality of future pixel values comprises holding three future pixel values.

58. The method of claim 57, wherein concurrently holding three future pixel values comprises concurrently holding red, green and blue future pixel values.

69. A device, comprising:

a pixel electrode;

a driving circuit coupled to said pixel electrode for driving said pixel electrode at a present pixel value, wherein the driving circuit includes a driving unit consisting of a single element; and

a holding unit contained within said driving unit for holding a future pixel value while said pixel electrode is at said present pixel value.

70. The device of claim 69, wherein said single element is a transistor being the driving unit and the holding unit.

71. The device of claim 69, wherein said driving circuit includes three driving units each consisting of a single element, wherein said holding unit is adapted to concurrently hold at least one of red, green and blue future pixel values.

72. The device of claim 71, wherein said future pixel values are one of red and a combination of red and blue.

73. A method of driving a pixel, comprising:

driving a pixel at a present pixel value using a pixel driving circuit; and

independently holding at least one future pixel value at a holding unit contained within said driving circuit while said pixel is at said present pixel value, wherein said pixel driving circuit comprises,

a first transistor having a first electrode connected to a first prescribed voltage,

a second transistor having a first electrode connected to a second electrode of the first transistor, and

a third transistor having a first electrode connected at a connection point to a second electrode of the second transistor and said pixel, wherein a second electrode of the third transistor is connected to a second prescribed voltage.